diff --git a/plasma/gpio/Makefile b/plasma/gpio/Makefile index caed95f..cf5891b 100644 --- a/plasma/gpio/Makefile +++ b/plasma/gpio/Makefile @@ -27,7 +27,7 @@ vpath %.S $(LIB_DIR) all: $(TARGET) clean: - -rm -rf *.o *.txt *.map *.lst *.bin opcodes_iram opcodes_ram test bootldr $(TARGET) + -rm -rf *.o *.txt *.map *.lst *.s *.bin opcodes_iram opcodes_ram test bootldr $(TARGET) $(TARGET): crt0.o $(TARGET).o no_os.o ddr_init.o $(LD) $(ILDFLAGS) -o $@ $^ diff --git a/plasma/gpio/gpio.c b/plasma/gpio/gpio.c index b9a41fd..7132b39 100644 --- a/plasma/gpio/gpio.c +++ b/plasma/gpio/gpio.c @@ -9,7 +9,7 @@ typedef unsigned short uint16; int main(void) { - volatile unsigned char *data8; + volatile unsigned char *data8; volatile unsigned short *data16; volatile unsigned int *data32; diff --git a/plasma/logic/Makefile b/plasma/logic/Makefile index 702fe27..3d3b2cf 100644 --- a/plasma/logic/Makefile +++ b/plasma/logic/Makefile @@ -1,13 +1,26 @@ DESIGN = plasma PINS = $(DESIGN).ucf DEVICE = xc3s500e-VQ100-4 -#DEVICE = xc3s500e-fg320-4 BGFLAGS = -g TdoPin:PULLNONE -g DonePin:PULLUP \ -g CRC:enable -g StartUpClk:CCLK + SIM_CMD = /opt/cad/modeltech/bin/vsim SIM_COMP_SCRIPT = simulation/$(DESIGN)_TB.do SIMGEN_OPTIONS = -p $(FPGA_ARCH) -lang $(LANGUAGE) +SIMTOP = $(DESIGN)_tb +GHDL_SIM_OPT = --stop-time=1ms +SIMDIR = simu +GHDL_CMD = ghdl +GHDL_SIMU_FLAGS = --ieee=synopsys -P$$XILINX/ghdl/unisim --warn-no-vital-generic +GHDL_SYNTHESIS_FLAGS = --ieee=synopsys -P$$XILINX/ghdl/unisim --warn-no-vital-generic +GHDL_PANDR_FLAGS = --ieee=synopsys -P$$XILINX/ghdl/simprim --warn-no-vital-generic +VIEW_CMD = gtkwave +TESTBENCH_FILE = $(DESIGN)_TB.vhd +SYNT_TESTBENCH_FILE = $(DESIGN)_TB_syn.vhd +SYNTHESIS_FILE = simu/$(DESIGN)_synt.vhd +LIBRARY_FILE = mlite_pack.vhd + SRC_HDL = mlite_pack.vhd plasma.vhd ram_image.vhd alu.vhd control.vhd mem_ctrl.vhd mult.vhd shifter.vhd bus_mux.vhd mlite_cpu.vhd pc_next.vhd pipeline.vhd reg_bank.vhd uart.vhd all: bits @@ -22,7 +35,7 @@ clean: clean-build: rm -rf build -cleanall: clean +cleanall: clean clean_ghdl rm -rf build work $(DESIGN).bit bits: $(DESIGN).bit @@ -67,15 +80,36 @@ $(DESIGN).bit: build/project_r.ncd build/project_r.twr cd build && bitgen project_r.ncd -l -w $(BGFLAGS) @mv -f build/project_r.bit $@ -build/project_r.v: build/project_r.ncd - cd build && netgen -sim -ofmt vhdl project_r.ncd -pcf project.pcf && ngd2ver project.ngd -w project.v +build/project.vhd: build/project.ngc + cd build && netgen -w -ofmt vhdl project.ngc project.vhd sim: cd simulation; $(SIM_CMD) -do $(DESIGN)_TB.do -timesim: build/project_r.v - cd simulation; $(SIM_CMD) -do $(DESIGN)_TIMING_TB.do +ghdl-simu : ghdl-compil ghdl-run ghdl-view -sim: - cd simulation; $(SIM_CMD) -do $(DESIGN)_TB.do +ghdl-synthesis : ghdl-compil-synthesis ghdl-run ghdl-view + +ghdl-compil : + mkdir -p simu + $(GHDL_CMD) -i $(GHDL_SIMU_FLAGS) --workdir=simu --work=work $(TESTBENCH_FILE) $(LIBRARY_FILE) $(SRC_HDL) + $(GHDL_CMD) -m $(GHDL_SIMU_FLAGS) -fexplicit --workdir=simu --work=work $(SIMTOP) + @mv $(SIMTOP) simu/$(SIMTOP) + +ghdl-compil-synthesis: build/project.vhd + mkdir -p simu + cp build/project.vhd simu/$(DESIGN)_synt.vhd + $(GHDL_CMD) -i $(GHDL_SYNTHESIS_FLAGS) --workdir=simu --work=work $(SYNT_TESTBENCH_FILE) $(SYNTHESIS_FILE) + $(GHDL_CMD) -m $(GHDL_SYNTHESIS_FLAGS) --workdir=simu --work=work $(SIMTOP) + @mv $(SIMTOP) simu/$(SIMTOP) + +ghdl-run : + @$(SIMDIR)/$(SIMTOP) $(GHDL_SIM_OPT) --vcdgz=$(SIMDIR)/$(SIMTOP).vcdgz + +ghdl-view: + gunzip --stdout $(SIMDIR)/$(SIMTOP).vcdgz | $(VIEW_CMD) --vcd + +clean_ghdl : + $(GHDL_CMD) --clean --workdir=simu + -rm -rf simu diff --git a/plasma/logic/mlite_pack.vhd b/plasma/logic/mlite_pack.vhd index 45b3fc6..527cc69 100644 --- a/plasma/logic/mlite_pack.vhd +++ b/plasma/logic/mlite_pack.vhd @@ -13,6 +13,7 @@ library ieee; use ieee.numeric_std.all; use ieee.std_logic_1164.all; + package mlite_pack is constant ZERO : std_logic_vector(31 downto 0) := "00000000000000000000000000000000"; diff --git a/plasma/logic/plasma.vhd b/plasma/logic/plasma.vhd index 1985856..7da31db 100644 --- a/plasma/logic/plasma.vhd +++ b/plasma/logic/plasma.vhd @@ -1,4 +1,3 @@ ---------------------------------------------------------------------- -- TITLE: Plasma (CPU core with memory) -- AUTHOR: Steve Rhoads (rhoadss@yahoo.com) -- DATE CREATED: 6/4/02 diff --git a/plasma/logic/plasma_TB.vhd b/plasma/logic/plasma_TB.vhd index f841c3d..8f6fca3 100644 --- a/plasma/logic/plasma_TB.vhd +++ b/plasma/logic/plasma_TB.vhd @@ -11,15 +11,14 @@ --------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; -use work.mlite_pack.all; +--use work.mlite_pack.all; use ieee.std_logic_unsigned.all; -entity tbench is +entity plasma_tb is end; --entity tbench -architecture logic of tbench is - constant memory_type : string := - "TRI_PORT_X"; +architecture logic of plasma_tb is + constant memory_type : string := "TRI_PORT_X"; signal clk_in : std_logic := '1'; signal rst_in : std_logic := '0'; @@ -33,6 +32,22 @@ architecture logic of tbench is signal TxD : std_logic; signal RxD : std_logic; + component plasma + generic(memory_type : string := "XILINX_X16"; log_file : string := "UNUSED"); + port(clk_in : in std_logic; + rst_in : in std_logic; + uart_write : out std_logic; + uart_read : in std_logic; + + addr : in std_logic_vector(12 downto 0); + sram_data : in std_logic_vector(7 downto 0); + nwe : in std_logic; + noe : in std_logic; + ncs : in std_logic; + irq_pin : out std_logic; + led : out std_logic); + end component; --plasma + begin --architecture clk_in <= not clk_in after 50 ns; rst_in <= '1' after 500 ns; @@ -40,7 +55,7 @@ begin --architecture u1_plasma: plasma - generic map (memory_type => memory_type) + generic map (memory_type => memory_type, log_file => "UNUSED") PORT MAP ( clk_in => clk_in, rst_in => rst_in, diff --git a/plasma/logic/plasma_TB_syn.vhd b/plasma/logic/plasma_TB_syn.vhd new file mode 100644 index 0000000..a333a8e --- /dev/null +++ b/plasma/logic/plasma_TB_syn.vhd @@ -0,0 +1,70 @@ +--------------------------------------------------------------------- +-- TITLE: Test Bench +-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com) +-- DATE CREATED: 4/21/01 +-- FILENAME: tbench.vhd +-- PROJECT: Plasma CPU core +-- COPYRIGHT: Software placed into the public domain by the author. +-- Software 'as is' without warranty. Author liable for nothing. +-- DESCRIPTION: +-- This entity provides a test bench for testing the Plasma CPU core. +--------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; + +entity plasma_tb is +end; --entity tbench + +architecture logic of plasma_tb is + constant memory_type : string := "TRI_PORT_X"; + + signal clk_in : std_logic := '1'; + signal rst_in : std_logic := '0'; + signal addr : std_logic_vector(12 downto 0); + signal sram_data : std_logic_vector(7 downto 0); + signal nwe : std_logic; + signal noe : std_logic; + signal ncs : std_logic; + signal irq_pin : std_logic; + signal led : std_logic; + signal TxD : std_logic; + signal RxD : std_logic; + + component plasma + port(clk_in : in std_logic; + rst_in : in std_logic; + uart_write : out std_logic; + uart_read : in std_logic; + + addr : in std_logic_vector(12 downto 0); + sram_data : in std_logic_vector(7 downto 0); + nwe : in std_logic; + noe : in std_logic; + ncs : in std_logic; + irq_pin : out std_logic; + led : out std_logic); + end component; --plasma + +begin --architecture + clk_in <= not clk_in after 50 ns; + rst_in <= '1' after 500 ns; + RxD <= '1'; + + + u1_plasma: plasma + PORT MAP ( + clk_in => clk_in, + rst_in => rst_in, + uart_read => RxD, + uart_write => TxD, + addr => addr, + sram_data => sram_data, + nwe => nwe, + noe => noe, + ncs => ncs, + irq_pin => irq_pin, + led => led + ); + +end; --architecture logic diff --git a/plasma/logic/tbench.vhd b/plasma/logic/tbench.vhd deleted file mode 100644 index 700c123..0000000 --- a/plasma/logic/tbench.vhd +++ /dev/null @@ -1,119 +0,0 @@ ---------------------------------------------------------------------- --- TITLE: Test Bench --- AUTHOR: Steve Rhoads (rhoadss@yahoo.com) --- DATE CREATED: 4/21/01 --- FILENAME: tbench.vhd --- PROJECT: Plasma CPU core --- COPYRIGHT: Software placed into the public domain by the author. --- Software 'as is' without warranty. Author liable for nothing. --- DESCRIPTION: --- This entity provides a test bench for testing the Plasma CPU core. ---------------------------------------------------------------------- -library ieee; -use ieee.std_logic_1164.all; -use work.mlite_pack.all; -use ieee.std_logic_unsigned.all; - -entity tbench is -end; --entity tbench - -architecture logic of tbench is - constant memory_type : string := - "TRI_PORT_X"; --- "DUAL_PORT_"; --- "ALTERA_LPM"; --- "XILINX_16X"; - - constant log_file : string := --- "UNUSED"; - "output.txt"; - - signal clk : std_logic := '1'; - signal reset : std_logic := '1'; - signal interrupt : std_logic := '0'; - signal mem_write : std_logic; - signal address : std_logic_vector(31 downto 2); - signal data_write : std_logic_vector(31 downto 0); - signal data_read : std_logic_vector(31 downto 0); - signal pause1 : std_logic := '0'; - signal pause2 : std_logic := '0'; - signal pause : std_logic; - signal no_ddr_start: std_logic; - signal no_ddr_stop : std_logic; - signal byte_we : std_logic_vector(3 downto 0); - signal uart_write : std_logic; - signal gpioA_in : std_logic_vector(31 downto 0) := (others => '0'); -begin --architecture - --Uncomment the line below to test interrupts - interrupt <= '1' after 20 us when interrupt = '0' else '0' after 445 ns; - - clk <= not clk after 50 ns; - reset <= '0' after 500 ns; - pause1 <= '1' after 700 ns when pause1 = '0' else '0' after 200 ns; - pause2 <= '1' after 300 ns when pause2 = '0' else '0' after 200 ns; - pause <= pause1 or pause2; - gpioA_in(20) <= not gpioA_in(20) after 200 ns; --E_RX_CLK - gpioA_in(19) <= not gpioA_in(19) after 20 us; --E_RX_DV - gpioA_in(18 downto 15) <= gpioA_in(18 downto 15) + 1 after 400 ns; --E_RX_RXD - gpioA_in(14) <= not gpioA_in(14) after 200 ns; --E_TX_CLK - - u1_plasma: plasma - generic map (memory_type => memory_type, - ethernet => '1', - use_cache => '1', - log_file => log_file) - PORT MAP ( - clk => clk, - reset => reset, - uart_read => uart_write, - uart_write => uart_write, - - address => address, - byte_we => byte_we, - data_write => data_write, - data_read => data_read, - mem_pause_in => pause, - no_ddr_start => no_ddr_start, - no_ddr_stop => no_ddr_stop, - - gpio0_out => open, - gpioA_in => gpioA_in); - - dram_proc: process(clk, address, byte_we, data_write, pause) - constant ADDRESS_WIDTH : natural := 16; - type storage_array is - array(natural range 0 to (2 ** ADDRESS_WIDTH) / 4 - 1) of - std_logic_vector(31 downto 0); - variable storage : storage_array; - variable data : std_logic_vector(31 downto 0); - variable index : natural := 0; - begin - index := conv_integer(address(ADDRESS_WIDTH-1 downto 2)); - data := storage(index); - - if byte_we(0) = '1' then - data(7 downto 0) := data_write(7 downto 0); - end if; - if byte_we(1) = '1' then - data(15 downto 8) := data_write(15 downto 8); - end if; - if byte_we(2) = '1' then - data(23 downto 16) := data_write(23 downto 16); - end if; - if byte_we(3) = '1' then - data(31 downto 24) := data_write(31 downto 24); - end if; - - if rising_edge(clk) then - if address(30 downto 28) = "001" and byte_we /= "0000" then - storage(index) := data; - end if; - end if; - - if pause = '0' then - data_read <= data; - end if; - end process; - - -end; --architecture logic