Adding Xc3sprog ported to SAKC

Adding FPGA sram hdl code and user space code
Fixing some errors:
LCD's pinout connector is swapped
FPGA TDI SIGNAL must be routed to another pin (C14), right now is DQMH
Remove R11
Check JZ4725 symbol's component (PORTD is wrong)
Adding PB2 and PB3
wiring ADC's vref to external connector
Adding power LED
Adding CPU Led

Examples/sram/logic/Makefile

@@ -0,0 +1,74 @@
+DESIGN          = sram_bus
+PINS            = sram_bus.ucf
+DEVICE          = xc3s250e-VQ100-4
+BGFLAGS         = -g TdoPin:PULLNONE -g DonePin:PULLUP \
+                  -g CRC:enable -g StartUpClk:CCLK
+
+SIM_CMD         = /opt/cad/modeltech/bin/vsim 
+SIM_COMP_SCRIPT = simulation/$(DESIGN)_TB.do
+#SIM_INIT_SCRIPT = simulation/$(DESIGN)_init.do
+SIMGEN_OPTIONS  = -p $(FPGA_ARCH) -lang $(LANGUAGE)
+SAKC_IP         = 192.168.254.101
+
+SRC             = sram_bus.v 
+ 
+all:            bits
+
+remake:         clean-build all
+
+clean:
+	rm -f *~ */*~ a.out *.log *.key *.edf *.ps trace.dat
+	rm *.bit
+
+clean-build: clean
+	rm -rf build
+
+cleanall:   clean
+	rm -rf build $(DESIGN).bit
+
+bits:           $(DESIGN).bit
+
+#
+# Synthesis
+#
+build/project.src:
+	@[ -d build ] || mkdir build
+	@rm -f $@
+	for i in $(SRC); do echo verilog work ../$$i >> $@; done
+	for i in $(SRC_HDL); do echo VHDL work ../$$i >> $@; done
+
+build/project.xst: build/project.src
+	echo "run" > $@
+	echo "-top $(DESIGN) " >> $@
+	echo "-p $(DEVICE)" >> $@
+	echo "-opt_mode Area" >> $@
+	echo "-opt_level 1" >> $@
+	echo "-ifn project.src" >> $@
+	echo "-ifmt mixed" >> $@
+	echo "-ofn project.ngc" >> $@
+	echo "-ofmt NGC" >> $@
+	echo "-rtlview yes" >> $@
+
+build/project.ngc: build/project.xst $(SRC)
+	cd build && xst -ifn project.xst -ofn project.log
+
+build/project.ngd: build/project.ngc $(PINS)
+	cd build && ngdbuild -p $(DEVICE) project.ngc -uc ../$(PINS)
+
+build/project.ncd: build/project.ngd
+	cd build && map -pr b -p $(DEVICE) project
+
+build/project_r.ncd: build/project.ncd
+	cd build && par -w project project_r.ncd
+
+build/project_r.twr: build/project_r.ncd
+	cd build && trce -v 25 project_r.ncd project.pcf
+
+$(DESIGN).bit:  build/project_r.ncd build/project_r.twr
+	cd build && bitgen project_r.ncd -l -w $(BGFLAGS)
+	@mv -f build/project_r.bit $@
+sim: 
+	cd simulation; $(SIM_CMD) -do $(DESIGN)_TB.do 
+
+upload: $(DESIGN).bit
+	scp $(DESIGN).bit root@$(SAKC_IP): 

Examples/sram/logic/sram_bus.ucf

@@ -0,0 +1,43 @@
+NET clk   LOC = "P38";
+NET reset LOC = "P71";
+NET led   LOC = "P44";
+
+#ADDRESS BUS
+NET "addr<12>" LOC = "P90";
+NET "addr<11>" LOC = "P91";
+NET "addr<10>" LOC = "P85";
+NET "addr<9>" LOC = "P92";
+NET "addr<8>" LOC = "P94";
+NET "addr<7>" LOC = "P95";
+NET "addr<6>" LOC = "P98";
+NET "addr<5>" LOC = "P3";
+NET "addr<4>" LOC = "P2";
+NET "addr<3>" LOC = "P78";
+NET "addr<2>" LOC = "P79";
+NET "addr<1>" LOC = "P83";
+NET "addr<0>" LOC = "P84";
+
+#DATA BUS
+NET "sram_data<7>"  LOC = "P4";
+NET "sram_data<6>"  LOC = "P5";
+NET "sram_data<5>"  LOC = "P9";
+NET "sram_data<4>"  LOC = "P10";
+NET "sram_data<3>"  LOC = "P11";
+NET "sram_data<2>"  LOC = "P12";
+NET "sram_data<1>"  LOC = "P15";
+NET "sram_data<0>"  LOC = "P16";
+
+#CONTROL BUS
+NET "nwe"   LOC = "P88";
+NET "noe"   LOC = "P86";
+NET "ncs"   LOC = "P69";
+
+#ADC
+#NET "ADC_EOC"    LOC = "P17";
+#NET "ADC_SCLK"   LOC = "P18";
+#NET "ADC_SDIN"   LOC = "P22";
+#NET "ADC_SDOUT"  LOC = "P23";
+#NET "ADC_CS"     LOC = "P24";
+#NET "ADC_CSTART" LOC = "P26";
+
+

Examples/sram/logic/sram_bus.v

@@ -0,0 +1,75 @@
+`timescale 1ns / 1ps
+module sram_bus(clk, sram_data, addr, nwe, ncs, noe, reset, led);
+  parameter     B = (7);
+
+  input            clk, addr, nwe, ncs, noe, reset;
+  inout [B:0]      sram_data;
+  output           led;
+
+// Internal conection
+  wire    led;
+
+  // synchronize signals                               
+  reg    sncs, snwe;
+  reg    [12:0] buffer_addr;
+  reg    [B:0] buffer_data;  
+
+  // interfaz fpga signals
+  wire   [12:0] addr;
+	
+  // bram interfaz signals
+  reg    we;
+  reg    w_st;
+
+  reg    [B:0] wdBus;
+  wire   [B:0] rdBus;
+
+  // interefaz signals assignments
+  wire   T = ~noe | ncs;
+  assign sram_data = T?8'bZ:rdBus;
+  
+  //--------------------------------------------------------------------------
+
+  // synchronize assignment
+  always  @(negedge clk)
+  begin
+    sncs   <= ncs;
+    snwe   <= nwe;
+    buffer_data <= sram_data;
+    buffer_addr <= addr;
+  end
+
+  // write access cpu to bram
+  always @(posedge clk)
+    if(reset) {w_st, we, wdBus} <= 0;
+      else begin
+        wdBus <= buffer_data;
+        case (w_st)
+          0: begin
+              we <= 0;
+              if(sncs | snwe) w_st <= 1;
+          end
+          1: begin
+            if(~(sncs | snwe)) begin
+              we    <= 1;
+              w_st  <= 0;
+            end	
+            else we <= 0;
+          end
+        endcase
+      end
+
+RAMB16_S18 ba0( .CLK(~clk), .EN(1'b1),   .SSR(1'b0),      .ADDR(buffer_addr), 
+                .WE(we),    .DIP(2'b00), .DI(wdBus), .DO(rdBus) );  
+
+  reg [32:0]  counter;
+  always @(posedge clk) begin
+    if (reset)
+      counter <= {32{1'b0}};
+    else
+      counter <= counter + 1;
+  end 
+  assign led = counter[24];
+
+endmodule
+