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mirror of git://projects.qi-hardware.com/nn-usb-fpga.git synced 2025-04-21 12:27:27 +03:00

Adding Xc3sprog ported to SAKC

Adding FPGA sram hdl code and user space code
Fixing some errors:
LCD's pinout connector is swapped
FPGA TDI SIGNAL must be routed to another pin (C14), right now is DQMH
Remove R11
Check JZ4725 symbol's component (PORTD is wrong)
Adding PB2 and PB3
wiring ADC's vref to external connector
Adding power LED
Adding CPU Led
This commit is contained in:
Carlos Camargo
2010-03-17 15:42:11 -05:00
parent 307c5f471b
commit a7c692d3f0
55 changed files with 3219 additions and 0 deletions

View File

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`timescale 1ns / 1ps
module sram_bus(clk, sram_data, addr, nwe, ncs, noe, reset, led);
parameter B = (7);
input clk, addr, nwe, ncs, noe, reset;
inout [B:0] sram_data;
output led;
// Internal conection
wire led;
// synchronize signals
reg sncs, snwe;
reg [12:0] buffer_addr;
reg [B:0] buffer_data;
// interfaz fpga signals
wire [12:0] addr;
// bram interfaz signals
reg we;
reg w_st;
reg [B:0] wdBus;
wire [B:0] rdBus;
// interefaz signals assignments
wire T = ~noe | ncs;
assign sram_data = T?8'bZ:rdBus;
//--------------------------------------------------------------------------
// synchronize assignment
always @(negedge clk)
begin
sncs <= ncs;
snwe <= nwe;
buffer_data <= sram_data;
buffer_addr <= addr;
end
// write access cpu to bram
always @(posedge clk)
if(reset) {w_st, we, wdBus} <= 0;
else begin
wdBus <= buffer_data;
case (w_st)
0: begin
we <= 0;
if(sncs | snwe) w_st <= 1;
end
1: begin
if(~(sncs | snwe)) begin
we <= 1;
w_st <= 0;
end
else we <= 0;
end
endcase
end
RAMB16_S18 ba0( .CLK(~clk), .EN(1'b1), .SSR(1'b0), .ADDR(buffer_addr),
.WE(we), .DIP(2'b00), .DI(wdBus), .DO(rdBus) );
reg [32:0] counter;
always @(posedge clk) begin
if (reset)
counter <= {32{1'b0}};
else
counter <= counter + 1;
end
assign led = counter[24];
endmodule