mirror of
git://projects.qi-hardware.com/nn-usb-fpga.git
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Fixing some examples, adding scripts for compiling xilinx libs with ghdl
This commit is contained in:
Carlos Camargo
33
Examples/sram_gpio/logic/sim/unisims/BUFG.v
Normal file
33
Examples/sram_gpio/logic/sim/unisims/BUFG.v
Normal file
@@ -0,0 +1,33 @@
|
||||
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/BUFG.v,v 1.5.158.1 2007/03/09 18:13:02 patrickp Exp $
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
// Copyright (c) 1995/2004 Xilinx, Inc.
|
||||
// All Right Reserved.
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
// ____ ____
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||||
// / /\/ /
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// /___/ \ / Vendor : Xilinx
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||||
// \ \ \/ Version : 8.1i (I.13)
|
||||
// \ \ Description : Xilinx Functional Simulation Library Component
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// / / Global Clock Buffer
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// /___/ /\ Filename : BUFG.v
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||||
// \ \ / \ Timestamp : Thu Mar 25 16:42:14 PST 2004
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// \___\/\___\
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//
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// Revision:
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// 03/23/04 - Initial version.
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// End Revision
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`timescale 100 ps / 10 ps
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module BUFG (O, I);
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output O;
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input I;
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buf B1 (O, I);
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endmodule
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1731
Examples/sram_gpio/logic/sim/unisims/DCM.v
Normal file
1731
Examples/sram_gpio/logic/sim/unisims/DCM.v
Normal file
File diff suppressed because it is too large
Load Diff
1244
Examples/sram_gpio/logic/sim/unisims/DCM_SP.v
Normal file
1244
Examples/sram_gpio/logic/sim/unisims/DCM_SP.v
Normal file
File diff suppressed because it is too large
Load Diff
102
Examples/sram_gpio/logic/sim/unisims/FDDRRSE.v
Normal file
102
Examples/sram_gpio/logic/sim/unisims/FDDRRSE.v
Normal file
@@ -0,0 +1,102 @@
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// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/FDDRRSE.v,v 1.15.48.1 2007/03/09 18:13:02 patrickp Exp $
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///////////////////////////////////////////////////////////////////////////////
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||||
// Copyright (c) 1995/2004 Xilinx, Inc.
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// All Right Reserved.
|
||||
///////////////////////////////////////////////////////////////////////////////
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||||
// ____ ____
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||||
// / /\/ /
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// /___/ \ / Vendor : Xilinx
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// \ \ \/ Version : 8.1i (I.27)
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// \ \ Description : Xilinx Functional Simulation Library Component
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// / / Dual Data Rate D Flip-Flop with Synchronous Reset and Set and Clock Enable
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// /___/ /\ Filename : FDDRRSE.v
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// \ \ / \ Timestamp : Thu Mar 25 16:42:16 PST 2004
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// \___\/\___\
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//
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// Revision:
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// 03/23/04 - Initial version.
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// 02/04/05 - Rev 0.0.1 Remove input/output bufs; Seperate GSR from clock block.
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// 05/06/05 - Remove internal input data strobe and add to the output. (CR207678)
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// 10/20/05 - Add set & reset check to main block. (CR219794)
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// 10/28/05 - combine strobe block and data block. (CR220298).
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// 2/07/06 - Remove set & reset from main block and add specify block (CR225119)
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// 2/10/06 - Change Q from reg to wire (CR 225613)
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// End Revision
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`timescale 1 ps / 1 ps
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module FDDRRSE (Q, C0, C1, CE, D0, D1, R, S);
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parameter INIT = 1'h0;
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output Q;
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input C0, C1, CE, D0, D1, R, S;
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wire Q;
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reg q_out;
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reg q0_out, q1_out;
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reg C0_tmp, C1_tmp;
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initial begin
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q_out = INIT;
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q0_out = INIT;
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q1_out = INIT;
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C0_tmp = 0;
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C1_tmp = 0;
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end
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assign Q = q_out;
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always @(posedge C0)
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if (CE == 1 || R == 1 || S == 1) begin
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C0_tmp <= 1;
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C0_tmp <= #100 0;
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end
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always @(posedge C1)
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if (CE == 1 || R == 1 || S == 1) begin
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C1_tmp <= 1;
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C1_tmp <= #100 0;
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end
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always @(posedge C0)
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if (R)
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q0_out <= 0;
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else if (S)
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q0_out <= 1;
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else if (CE)
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q0_out <= D0;
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always @(posedge C1)
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if (R)
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q1_out <= 0;
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else if (S)
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q1_out <= 1;
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else if (CE)
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q1_out <= D1;
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always @(posedge C0_tmp or posedge C1_tmp )
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if (C1_tmp)
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q_out = q1_out;
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else
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q_out = q0_out;
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specify
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if (R)
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(posedge C0 => (Q +: 1'b0)) = (100, 100);
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if (!R && S)
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(posedge C0 => (Q +: 1'b1)) = (100, 100);
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if (!R && !S && CE)
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(posedge C0 => (Q +: D0)) = (100, 100);
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if (R)
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(posedge C1 => (Q +: 1'b0)) = (100, 100);
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if (!R && S)
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(posedge C1 => (Q +: 1'b1)) = (100, 100);
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if (!R && !S && CE)
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(posedge C1 => (Q +: D1)) = (100, 100);
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endspecify
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endmodule
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521
Examples/sram_gpio/logic/sim/unisims/RAMB16_S2.v
Normal file
521
Examples/sram_gpio/logic/sim/unisims/RAMB16_S2.v
Normal file
@@ -0,0 +1,521 @@
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// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/RAMB16_S2.v,v 1.7.158.1 2007/03/09 18:13:18 patrickp Exp $
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///////////////////////////////////////////////////////////////////////////////
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// Copyright (c) 1995/2005 Xilinx, Inc.
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// All Right Reserved.
|
||||
///////////////////////////////////////////////////////////////////////////////
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||||
// ____ ____
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||||
// / /\/ /
|
||||
// /___/ \ / Vendor : Xilinx
|
||||
// \ \ \/ Version : 8.1i (I.13)
|
||||
// \ \ Description : Xilinx Functional Simulation Library Component
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||||
// / / 16K-Bit Data and 2K-Bit Parity Single Port Block RAM
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||||
// /___/ /\ Filename : RAMB16_S2.v
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// \ \ / \ Timestamp : Thu Mar 10 16:43:35 PST 2005
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// \___\/\___\
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//
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// Revision:
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// 03/23/04 - Initial version.
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// End Revision
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||||
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`ifdef legacy_model
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`timescale 1 ps / 1 ps
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module RAMB16_S2 (DO, ADDR, CLK, DI, EN, SSR, WE);
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parameter INIT = 2'h0;
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parameter SRVAL = 2'h0;
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parameter WRITE_MODE = "WRITE_FIRST";
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parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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||||
parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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||||
parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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||||
parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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||||
parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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||||
parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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||||
parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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||||
parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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||||
parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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||||
parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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||||
parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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||||
parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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||||
parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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||||
parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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||||
parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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||||
parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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||||
parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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||||
parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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||||
parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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||||
parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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||||
parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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||||
parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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||||
parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
|
||||
output [1:0] DO;
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reg do0_out, do1_out;
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input [12:0] ADDR;
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input [1:0] DI;
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input EN, CLK, WE, SSR;
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||||
|
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reg [18431:0] mem;
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reg [8:0] count;
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||||
reg [1:0] wr_mode;
|
||||
|
||||
wire [12:0] addr_int;
|
||||
wire [1:0] di_int;
|
||||
wire en_int, clk_int, we_int, ssr_int;
|
||||
|
||||
tri0 GSR = glbl.GSR;
|
||||
|
||||
always @(GSR)
|
||||
if (GSR) begin
|
||||
assign do0_out = INIT[0];
|
||||
assign do1_out = INIT[1];
|
||||
end
|
||||
else begin
|
||||
deassign do0_out;
|
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deassign do1_out;
|
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end
|
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|
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buf b_do_out0 (DO[0], do0_out);
|
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buf b_do_out1 (DO[1], do1_out);
|
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buf b_addr_0 (addr_int[0], ADDR[0]);
|
||||
buf b_addr_1 (addr_int[1], ADDR[1]);
|
||||
buf b_addr_2 (addr_int[2], ADDR[2]);
|
||||
buf b_addr_3 (addr_int[3], ADDR[3]);
|
||||
buf b_addr_4 (addr_int[4], ADDR[4]);
|
||||
buf b_addr_5 (addr_int[5], ADDR[5]);
|
||||
buf b_addr_6 (addr_int[6], ADDR[6]);
|
||||
buf b_addr_7 (addr_int[7], ADDR[7]);
|
||||
buf b_addr_8 (addr_int[8], ADDR[8]);
|
||||
buf b_addr_9 (addr_int[9], ADDR[9]);
|
||||
buf b_addr_10 (addr_int[10], ADDR[10]);
|
||||
buf b_addr_11 (addr_int[11], ADDR[11]);
|
||||
buf b_addr_12 (addr_int[12], ADDR[12]);
|
||||
buf b_di_0 (di_int[0], DI[0]);
|
||||
buf b_di_1 (di_int[1], DI[1]);
|
||||
buf b_en (en_int, EN);
|
||||
buf b_clk (clk_int, CLK);
|
||||
buf b_we (we_int, WE);
|
||||
buf b_ssr (ssr_int, SSR);
|
||||
|
||||
initial begin
|
||||
for (count = 0; count < 256; count = count + 1) begin
|
||||
mem[count] <= INIT_00[count];
|
||||
mem[256 * 1 + count] <= INIT_01[count];
|
||||
mem[256 * 2 + count] <= INIT_02[count];
|
||||
mem[256 * 3 + count] <= INIT_03[count];
|
||||
mem[256 * 4 + count] <= INIT_04[count];
|
||||
mem[256 * 5 + count] <= INIT_05[count];
|
||||
mem[256 * 6 + count] <= INIT_06[count];
|
||||
mem[256 * 7 + count] <= INIT_07[count];
|
||||
mem[256 * 8 + count] <= INIT_08[count];
|
||||
mem[256 * 9 + count] <= INIT_09[count];
|
||||
mem[256 * 10 + count] <= INIT_0A[count];
|
||||
mem[256 * 11 + count] <= INIT_0B[count];
|
||||
mem[256 * 12 + count] <= INIT_0C[count];
|
||||
mem[256 * 13 + count] <= INIT_0D[count];
|
||||
mem[256 * 14 + count] <= INIT_0E[count];
|
||||
mem[256 * 15 + count] <= INIT_0F[count];
|
||||
mem[256 * 16 + count] <= INIT_10[count];
|
||||
mem[256 * 17 + count] <= INIT_11[count];
|
||||
mem[256 * 18 + count] <= INIT_12[count];
|
||||
mem[256 * 19 + count] <= INIT_13[count];
|
||||
mem[256 * 20 + count] <= INIT_14[count];
|
||||
mem[256 * 21 + count] <= INIT_15[count];
|
||||
mem[256 * 22 + count] <= INIT_16[count];
|
||||
mem[256 * 23 + count] <= INIT_17[count];
|
||||
mem[256 * 24 + count] <= INIT_18[count];
|
||||
mem[256 * 25 + count] <= INIT_19[count];
|
||||
mem[256 * 26 + count] <= INIT_1A[count];
|
||||
mem[256 * 27 + count] <= INIT_1B[count];
|
||||
mem[256 * 28 + count] <= INIT_1C[count];
|
||||
mem[256 * 29 + count] <= INIT_1D[count];
|
||||
mem[256 * 30 + count] <= INIT_1E[count];
|
||||
mem[256 * 31 + count] <= INIT_1F[count];
|
||||
mem[256 * 32 + count] <= INIT_20[count];
|
||||
mem[256 * 33 + count] <= INIT_21[count];
|
||||
mem[256 * 34 + count] <= INIT_22[count];
|
||||
mem[256 * 35 + count] <= INIT_23[count];
|
||||
mem[256 * 36 + count] <= INIT_24[count];
|
||||
mem[256 * 37 + count] <= INIT_25[count];
|
||||
mem[256 * 38 + count] <= INIT_26[count];
|
||||
mem[256 * 39 + count] <= INIT_27[count];
|
||||
mem[256 * 40 + count] <= INIT_28[count];
|
||||
mem[256 * 41 + count] <= INIT_29[count];
|
||||
mem[256 * 42 + count] <= INIT_2A[count];
|
||||
mem[256 * 43 + count] <= INIT_2B[count];
|
||||
mem[256 * 44 + count] <= INIT_2C[count];
|
||||
mem[256 * 45 + count] <= INIT_2D[count];
|
||||
mem[256 * 46 + count] <= INIT_2E[count];
|
||||
mem[256 * 47 + count] <= INIT_2F[count];
|
||||
mem[256 * 48 + count] <= INIT_30[count];
|
||||
mem[256 * 49 + count] <= INIT_31[count];
|
||||
mem[256 * 50 + count] <= INIT_32[count];
|
||||
mem[256 * 51 + count] <= INIT_33[count];
|
||||
mem[256 * 52 + count] <= INIT_34[count];
|
||||
mem[256 * 53 + count] <= INIT_35[count];
|
||||
mem[256 * 54 + count] <= INIT_36[count];
|
||||
mem[256 * 55 + count] <= INIT_37[count];
|
||||
mem[256 * 56 + count] <= INIT_38[count];
|
||||
mem[256 * 57 + count] <= INIT_39[count];
|
||||
mem[256 * 58 + count] <= INIT_3A[count];
|
||||
mem[256 * 59 + count] <= INIT_3B[count];
|
||||
mem[256 * 60 + count] <= INIT_3C[count];
|
||||
mem[256 * 61 + count] <= INIT_3D[count];
|
||||
mem[256 * 62 + count] <= INIT_3E[count];
|
||||
mem[256 * 63 + count] <= INIT_3F[count];
|
||||
end
|
||||
end
|
||||
|
||||
initial begin
|
||||
case (WRITE_MODE)
|
||||
"WRITE_FIRST" : wr_mode <= 2'b00;
|
||||
"READ_FIRST" : wr_mode <= 2'b01;
|
||||
"NO_CHANGE" : wr_mode <= 2'b10;
|
||||
default : begin
|
||||
$display("Attribute Syntax Error : The attribute WRITE_MODE on RAMB16_S2 instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE);
|
||||
$finish;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
|
||||
always @(posedge clk_int) begin
|
||||
if (en_int == 1'b1) begin
|
||||
if (ssr_int == 1'b1) begin
|
||||
do0_out <= SRVAL[0];
|
||||
do1_out <= SRVAL[1];
|
||||
end
|
||||
else begin
|
||||
if (we_int == 1'b1) begin
|
||||
if (wr_mode == 2'b00) begin
|
||||
do0_out <= di_int[0];
|
||||
do1_out <= di_int[1];
|
||||
end
|
||||
else if (wr_mode == 2'b01) begin
|
||||
do0_out <= mem[addr_int * 2 + 0];
|
||||
do1_out <= mem[addr_int * 2 + 1];
|
||||
end
|
||||
else begin
|
||||
do0_out <= do0_out;
|
||||
do1_out <= do1_out;
|
||||
end
|
||||
end
|
||||
else begin
|
||||
do0_out <= mem[addr_int * 2 + 0];
|
||||
do1_out <= mem[addr_int * 2 + 1];
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk_int) begin
|
||||
if (en_int == 1'b1 && we_int == 1'b1) begin
|
||||
mem[addr_int * 2 + 0] <= di_int[0];
|
||||
mem[addr_int * 2 + 1] <= di_int[1];
|
||||
end
|
||||
end
|
||||
|
||||
specify
|
||||
(CLK *> DO) = (100, 100);
|
||||
endspecify
|
||||
|
||||
endmodule
|
||||
|
||||
`else
|
||||
|
||||
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/RAMB16_S2.v,v 1.7.158.1 2007/03/09 18:13:18 patrickp Exp $
|
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///////////////////////////////////////////////////////////////////////////////
|
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// Copyright (c) 1995/2005 Xilinx, Inc.
|
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// All Right Reserved.
|
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///////////////////////////////////////////////////////////////////////////////
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// ____ ____
|
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// / /\/ /
|
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// /___/ \ / Vendor : Xilinx
|
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// \ \ \/ Version : 8.1i (I.13)
|
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// \ \ Description : Xilinx Timing Simulation Library Component
|
||||
// / / 16K-Bit Data and 2K-Bit Parity Single Port Block RAM
|
||||
// /___/ /\ Filename : RAMB16_S2.v
|
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// \ \ / \ Timestamp : Thu Mar 10 16:44:01 PST 2005
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// \___\/\___\
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//
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// Revision:
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// 03/23/04 - Initial version.
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// 03/10/05 - Initialized outputs.
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// End Revision
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`timescale 1 ps/1 ps
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|
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module RAMB16_S2 (DO, ADDR, CLK, DI, EN, SSR, WE);
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parameter INIT = 2'h0;
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parameter SRVAL = 2'h0;
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parameter WRITE_MODE = "WRITE_FIRST";
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|
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parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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output [1:0] DO;
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input [12:0] ADDR;
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input [1:0] DI;
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input EN, CLK, WE, SSR;
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reg [1:0] do_out = INIT[1:0];
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reg [1:0] mem [8191:0];
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reg [8:0] count, countp;
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reg [1:0] wr_mode;
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wire [12:0] addr_int;
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wire [1:0] di_int;
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wire en_int, clk_int, we_int, ssr_int;
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wire di_enable = en_int && we_int;
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tri0 GSR = glbl.GSR;
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wire gsr_int;
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buf b_gsr (gsr_int, GSR);
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buf b_do [1:0] (DO, do_out);
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buf b_addr [12:0] (addr_int, ADDR);
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buf b_di [1:0] (di_int, DI);
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buf b_en (en_int, EN);
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buf b_clk (clk_int, CLK);
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buf b_ssr (ssr_int, SSR);
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buf b_we (we_int, WE);
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always @(gsr_int)
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if (gsr_int) begin
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assign {do_out} = INIT;
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||||
end
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else begin
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||||
deassign do_out;
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||||
end
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initial begin
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for (count = 0; count < 128; count = count + 1) begin
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mem[count] = INIT_00[(count * 2) +: 2];
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mem[128 * 1 + count] = INIT_01[(count * 2) +: 2];
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mem[128 * 2 + count] = INIT_02[(count * 2) +: 2];
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mem[128 * 3 + count] = INIT_03[(count * 2) +: 2];
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mem[128 * 4 + count] = INIT_04[(count * 2) +: 2];
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mem[128 * 5 + count] = INIT_05[(count * 2) +: 2];
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mem[128 * 6 + count] = INIT_06[(count * 2) +: 2];
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mem[128 * 7 + count] = INIT_07[(count * 2) +: 2];
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mem[128 * 8 + count] = INIT_08[(count * 2) +: 2];
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mem[128 * 9 + count] = INIT_09[(count * 2) +: 2];
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mem[128 * 10 + count] = INIT_0A[(count * 2) +: 2];
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mem[128 * 11 + count] = INIT_0B[(count * 2) +: 2];
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mem[128 * 12 + count] = INIT_0C[(count * 2) +: 2];
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mem[128 * 13 + count] = INIT_0D[(count * 2) +: 2];
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mem[128 * 14 + count] = INIT_0E[(count * 2) +: 2];
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mem[128 * 15 + count] = INIT_0F[(count * 2) +: 2];
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mem[128 * 16 + count] = INIT_10[(count * 2) +: 2];
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mem[128 * 17 + count] = INIT_11[(count * 2) +: 2];
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mem[128 * 18 + count] = INIT_12[(count * 2) +: 2];
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mem[128 * 19 + count] = INIT_13[(count * 2) +: 2];
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mem[128 * 20 + count] = INIT_14[(count * 2) +: 2];
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mem[128 * 21 + count] = INIT_15[(count * 2) +: 2];
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mem[128 * 22 + count] = INIT_16[(count * 2) +: 2];
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mem[128 * 23 + count] = INIT_17[(count * 2) +: 2];
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mem[128 * 24 + count] = INIT_18[(count * 2) +: 2];
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mem[128 * 25 + count] = INIT_19[(count * 2) +: 2];
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mem[128 * 26 + count] = INIT_1A[(count * 2) +: 2];
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mem[128 * 27 + count] = INIT_1B[(count * 2) +: 2];
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mem[128 * 28 + count] = INIT_1C[(count * 2) +: 2];
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mem[128 * 29 + count] = INIT_1D[(count * 2) +: 2];
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mem[128 * 30 + count] = INIT_1E[(count * 2) +: 2];
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mem[128 * 31 + count] = INIT_1F[(count * 2) +: 2];
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mem[128 * 32 + count] = INIT_20[(count * 2) +: 2];
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mem[128 * 33 + count] = INIT_21[(count * 2) +: 2];
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mem[128 * 34 + count] = INIT_22[(count * 2) +: 2];
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mem[128 * 35 + count] = INIT_23[(count * 2) +: 2];
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mem[128 * 36 + count] = INIT_24[(count * 2) +: 2];
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mem[128 * 37 + count] = INIT_25[(count * 2) +: 2];
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mem[128 * 38 + count] = INIT_26[(count * 2) +: 2];
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mem[128 * 39 + count] = INIT_27[(count * 2) +: 2];
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mem[128 * 40 + count] = INIT_28[(count * 2) +: 2];
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mem[128 * 41 + count] = INIT_29[(count * 2) +: 2];
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mem[128 * 42 + count] = INIT_2A[(count * 2) +: 2];
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mem[128 * 43 + count] = INIT_2B[(count * 2) +: 2];
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mem[128 * 44 + count] = INIT_2C[(count * 2) +: 2];
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||||
mem[128 * 45 + count] = INIT_2D[(count * 2) +: 2];
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mem[128 * 46 + count] = INIT_2E[(count * 2) +: 2];
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||||
mem[128 * 47 + count] = INIT_2F[(count * 2) +: 2];
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mem[128 * 48 + count] = INIT_30[(count * 2) +: 2];
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||||
mem[128 * 49 + count] = INIT_31[(count * 2) +: 2];
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||||
mem[128 * 50 + count] = INIT_32[(count * 2) +: 2];
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mem[128 * 51 + count] = INIT_33[(count * 2) +: 2];
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mem[128 * 52 + count] = INIT_34[(count * 2) +: 2];
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||||
mem[128 * 53 + count] = INIT_35[(count * 2) +: 2];
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||||
mem[128 * 54 + count] = INIT_36[(count * 2) +: 2];
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||||
mem[128 * 55 + count] = INIT_37[(count * 2) +: 2];
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||||
mem[128 * 56 + count] = INIT_38[(count * 2) +: 2];
|
||||
mem[128 * 57 + count] = INIT_39[(count * 2) +: 2];
|
||||
mem[128 * 58 + count] = INIT_3A[(count * 2) +: 2];
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||||
mem[128 * 59 + count] = INIT_3B[(count * 2) +: 2];
|
||||
mem[128 * 60 + count] = INIT_3C[(count * 2) +: 2];
|
||||
mem[128 * 61 + count] = INIT_3D[(count * 2) +: 2];
|
||||
mem[128 * 62 + count] = INIT_3E[(count * 2) +: 2];
|
||||
mem[128 * 63 + count] = INIT_3F[(count * 2) +: 2];
|
||||
end
|
||||
|
||||
end // initial begin
|
||||
|
||||
|
||||
initial begin
|
||||
case (WRITE_MODE)
|
||||
"WRITE_FIRST" : wr_mode <= 2'b00;
|
||||
"READ_FIRST" : wr_mode <= 2'b01;
|
||||
"NO_CHANGE" : wr_mode <= 2'b10;
|
||||
default : begin
|
||||
$display("Attribute Syntax Error : The Attribute WRITE_MODE on RAMB16_S2 instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE);
|
||||
$finish;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
|
||||
|
||||
always @(posedge clk_int) begin
|
||||
|
||||
if (en_int == 1'b1) begin
|
||||
|
||||
if (ssr_int == 1'b1) begin
|
||||
{do_out} <= #100 SRVAL;
|
||||
end
|
||||
else begin
|
||||
if (we_int == 1'b1) begin
|
||||
if (wr_mode == 2'b00) begin
|
||||
do_out <= #100 di_int;
|
||||
end
|
||||
else if (wr_mode == 2'b01) begin
|
||||
do_out <= #100 mem[addr_int];
|
||||
end
|
||||
end
|
||||
else begin
|
||||
do_out <= #100 mem[addr_int];
|
||||
end
|
||||
end
|
||||
|
||||
// memory
|
||||
if (we_int == 1'b1) begin
|
||||
mem[addr_int] <= di_int;
|
||||
end
|
||||
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
`endif
|
||||
1710
Examples/sram_gpio/logic/sim/unisims/RAMB16_S2_S18.v
Normal file
1710
Examples/sram_gpio/logic/sim/unisims/RAMB16_S2_S18.v
Normal file
File diff suppressed because it is too large
Load Diff
1536
Examples/sram_gpio/logic/sim/unisims/RAMB16_S2_S2.v
Normal file
1536
Examples/sram_gpio/logic/sim/unisims/RAMB16_S2_S2.v
Normal file
File diff suppressed because it is too large
Load Diff
1835
Examples/sram_gpio/logic/sim/unisims/RAMB16_S2_S36.v
Normal file
1835
Examples/sram_gpio/logic/sim/unisims/RAMB16_S2_S36.v
Normal file
File diff suppressed because it is too large
Load Diff
1555
Examples/sram_gpio/logic/sim/unisims/RAMB16_S2_S4.v
Normal file
1555
Examples/sram_gpio/logic/sim/unisims/RAMB16_S2_S4.v
Normal file
File diff suppressed because it is too large
Load Diff
1648
Examples/sram_gpio/logic/sim/unisims/RAMB16_S2_S9.v
Normal file
1648
Examples/sram_gpio/logic/sim/unisims/RAMB16_S2_S9.v
Normal file
File diff suppressed because it is too large
Load Diff
Reference in New Issue
Block a user