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Adding dual channel to scope example, fixing logic and QT source code.

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This commit is contained in:
Juan64Bits
2010-04-09 10:39:15 -05:00
parent 168c584b06
commit beca2e0bd3
36 changed files with 220 additions and 717 deletions
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30
Examples/ADC/logic/ADC_peripheral.v
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@@ -47,12 +47,12 @@ module ADC_peripheral( clk, reset, cs, ADC_EOC, ADC_CS, ADC_CSTART,
.DOB(), // Port B 8-bit Data Output
.DOPA(), // Port A 1-bit Parity Output
.DOPB(), // Port B 1-bit Parity Output
.ADDRA(addr), // Port A 11-bit Address Input
.ADDRB(addr2), // Port B 11-bit Address Input
.ADDRA(addr[10:0]), // Port A 11-bit Address Input
.ADDRB(addr2[10:0]), // Port B 11-bit Address Input
.CLKA(~clk), // Port A Clock
.CLKB(~clk), // Port B Clock
.DIA(wrBus), // Port A 8-bit Data Input
.DIB(wrBus2), // Port B 8-bit Data Input
.DIA(wrBus[7:0]), // Port A 8-bit Data Input
.DIB(wrBus2[7:0]), // Port B 8-bit Data Input
.DIPA(1'b0), // Port A 1-bit parity Input
.DIPB(1'b0), // Port-B 1-bit parity Input
.ENA(1'b1), // Port A RAM Enable Input
@@ -141,7 +141,7 @@ module ADC_peripheral( clk, reset, cs, ADC_EOC, ADC_CS, ADC_CSTART,
/**************************************************************************/
// REGISTER BANK: Write control
always @(posedge clk)
always @(negedge clk)
if(reset)
{CMD_START, CMD_TYP,CMD_ADC,SIZEB,we1} <= 0;
else if(we & cs) begin
@@ -175,21 +175,21 @@ module ADC_peripheral( clk, reset, cs, ADC_EOC, ADC_CS, ADC_CSTART,
// CONTROL
always @(posedge clk)
if(reset)
if(reset) begin
{w_st0, SPI_wr} <= 0;
ADC_CS <=1;
end
else begin
case (w_st0)
0: begin
rstStart <= 0; loadB <= 0; ADC_CS <=0; initB<=0;
rstStart <= 0; loadB <= 0; initB<=0;
if(CMD_START) begin
initB<=1;
ADC_CS <=0;
SPI_wr <= 1;
w_st0 <=1;
end
end
end
1: begin
SPI_wr <= 1; w_st0 <=2;
end
2: begin
SPI_wr <= 0;
if(!busy && ADC_EOC) begin
ADC_CS <=1;
@@ -198,12 +198,12 @@ module ADC_peripheral( clk, reset, cs, ADC_EOC, ADC_CS, ADC_CSTART,
w_st0<= 0;
end
else begin
loadB <= 1;
w_st0<= 0;
initB<=1;
w_st0<= 2;
end
end
end
2: begin loadB <= 1; w_st0<= 0; end
endcase
end