From de9acb468ba15672f9af810c4282f5f9b5ded833 Mon Sep 17 00:00:00 2001 From: Carlos Camargo Date: Tue, 4 May 2010 11:17:38 -0500 Subject: [PATCH] Adding write funtions to blink driver sample --- Examples/drivers/blink/blinker.c | 23 +++++- plasma/gpio/gpio.c | 3 + plasma/logic/Makefile | 6 +- plasma/logic/mlite_pack.vhd | 12 +-- plasma/logic/plasma.vhd | 133 +++++++------------------------ plasma/logic/ram_image.vhd | 44 +++++----- 6 files changed, 79 insertions(+), 142 deletions(-) diff --git a/Examples/drivers/blink/blinker.c b/Examples/drivers/blink/blinker.c index d856fa1..0ebbd0f 100644 --- a/Examples/drivers/blink/blinker.c +++ b/Examples/drivers/blink/blinker.c @@ -61,12 +61,30 @@ static int device_open(struct inode *inode, struct file *file) return SUCCESS; } +static ssize_t +device_write(struct file *filp, const char *buff, size_t count, loff_t * off) +{ + const char cmd = buff[0]; + + if(cmd=='Q') + { + printk(KERN_INFO "Q...\n"); + gpio_set_value(LED_PIN, 1); + } + else + if(cmd=='S'){ + printk(KERN_INFO "S...\n"); + gpio_set_value(LED_PIN, 0); + } + + return 1; +} + + static int device_release(struct inode *inode, struct file *file) { is_device_open = 0; - gpio_set_value(LED_PIN, 0); - module_put(THIS_MODULE); printk( KERN_INFO "Close BLINKER\n" ); @@ -76,6 +94,7 @@ static int device_release(struct inode *inode, struct file *file) struct file_operations fops = { .open = device_open, + .write = device_write, .release = device_release, }; diff --git a/plasma/gpio/gpio.c b/plasma/gpio/gpio.c index 6437aed..1ed421a 100644 --- a/plasma/gpio/gpio.c +++ b/plasma/gpio/gpio.c @@ -39,6 +39,9 @@ int main(void) data16++; *data32 = 0x30303030; + data32++; + *data32 = 0x31313131; + test8 = *data8; test16 = *data16; diff --git a/plasma/logic/Makefile b/plasma/logic/Makefile index aee3047..80de778 100644 --- a/plasma/logic/Makefile +++ b/plasma/logic/Makefile @@ -10,7 +10,7 @@ SIM_COMP_SCRIPT = simulation/$(DESIGN)_TB.do #SIM_INIT_SCRIPT = simulation/$(DESIGN)_init.do SIMGEN_OPTIONS = -p $(FPGA_ARCH) -lang $(LANGUAGE) -SRC_HDL = plasma.vhd alu.vhd control.vhd mem_ctrl.vhd mult.vhd shifter.vhd bus_mux.vhd ddr_ctrl.vhd mlite_cpu.vhd pc_next.vhd cache.vhd eth_dma.vhd mlite_pack.vhd pipeline.vhd reg_bank.vhd uart.vhd plasma_3e.vhd ram_image.vhd +SRC_HDL = plasma.vhd alu.vhd control.vhd mem_ctrl.vhd mult.vhd shifter.vhd bus_mux.vhd ddr_ctrl.vhd mlite_cpu.vhd pc_next.vhd cache.vhd eth_dma.vhd mlite_pack.vhd pipeline.vhd reg_bank.vhd uart.vhd ram_image.vhd all: bits @@ -53,8 +53,8 @@ build/project.xst: build/project.src build/project.ngc: build/project.xst $(SRC) cd build && xst -ifn project.xst -ofn project.log -build/project.ngd: build/project.ngc $(PINS) - cd build && ngdbuild -p $(DEVICE) project.ngc -uc ../$(PINS) +build/project.ngd: build/project.ngc #$(PINS) + cd build && ngdbuild -p $(DEVICE) project.ngc #-uc ../$(PINS) build/project.ncd: build/project.ngd cd build && map -pr b -p $(DEVICE) project diff --git a/plasma/logic/mlite_pack.vhd b/plasma/logic/mlite_pack.vhd index 17b2d9b..1aad7db 100644 --- a/plasma/logic/mlite_pack.vhd +++ b/plasma/logic/mlite_pack.vhd @@ -414,21 +414,15 @@ package mlite_pack is component plasma generic(memory_type : string := "XILINX_X16"; --"DUAL_PORT_" "ALTERA_LPM"; - log_file : string := "UNUSED"; - use_cache : std_logic := '0'); + log_file : string := "UNUSED"); port(clk : in std_logic; reset : in std_logic; uart_write : out std_logic; uart_read : in std_logic; - address : out std_logic_vector(31 downto 2); - byte_we : out std_logic_vector(3 downto 0); - data_write : out std_logic_vector(31 downto 0); data_read : in std_logic_vector(31 downto 0); - mem_pause_in : in std_logic; - - gpio0_out : out std_logic_vector(31 downto 0); - gpioA_in : in std_logic_vector(31 downto 0)); + mem_pause_in : in std_logic + ); end component; --plasma component ddr_ctrl diff --git a/plasma/logic/plasma.vhd b/plasma/logic/plasma.vhd index 1c03814..1d46897 100644 --- a/plasma/logic/plasma.vhd +++ b/plasma/logic/plasma.vhd @@ -20,14 +20,6 @@ -- 0x20000030 GPIO0 Out Set bits -- 0x20000040 GPIO0 Out Clear bits -- 0x20000050 GPIOA In --- 0x20000060 Counter --- IRQ bits: --- 7 GPIO31 --- 6 ^GPIO31 --- 3 Counter(18) --- 2 ^Counter(18) --- 1 ^UartWriteBusy --- 0 UartDataAvailable --------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; @@ -35,21 +27,16 @@ use work.mlite_pack.all; entity plasma is generic(memory_type : string := "XILINX_16X"; --"DUAL_PORT_" "ALTERA_LPM"; - log_file : string := "UNUSED"; - use_cache : std_logic := '0'); + log_file : string := "UNUSED"); port(clk : in std_logic; reset : in std_logic; uart_write : out std_logic; uart_read : in std_logic; - address : out std_logic_vector(31 downto 2); - byte_we : out std_logic_vector(3 downto 0); - data_write : out std_logic_vector(31 downto 0); data_read : in std_logic_vector(31 downto 0); - mem_pause_in : in std_logic; - gpio0_out : out std_logic_vector(31 downto 0); - gpioA_in : in std_logic_vector(31 downto 0)); + mem_pause_in : in std_logic + ); end; --entity plasma architecture logic of plasma is @@ -70,13 +57,11 @@ architecture logic of plasma is signal enable_uart_read : std_logic; signal enable_uart_write : std_logic; - signal gpio0_reg : std_logic_vector(31 downto 0); signal uart_write_busy : std_logic; signal uart_data_avail : std_logic; signal irq_mask_reg : std_logic_vector(7 downto 0); signal irq_status : std_logic_vector(7 downto 0); signal irq : std_logic; - signal counter_reg : std_logic_vector(31 downto 0); signal ram_enable : std_logic; signal ram_byte_we : std_logic_vector(3 downto 0); @@ -84,27 +69,10 @@ architecture logic of plasma is signal ram_data_w : std_logic_vector(31 downto 0); signal ram_data_r : std_logic_vector(31 downto 0); - signal cache_check : std_logic; - signal cache_checking : std_logic; - signal cache_miss : std_logic; - signal cache_hit : std_logic; - begin --architecture - write_enable <= '1' when cpu_byte_we /= "0000" else '0'; - mem_busy <= mem_pause_in; - cache_hit <= cache_checking and not cache_miss; - cpu_pause <= '0'; --(uart_write_busy and enable_uart and write_enable) or --UART busy --- cache_miss or --Cache wait --- (cpu_address(28) and not cache_hit and mem_busy); --DDR or flash --- gpio0_out(31 downto 29) <= gpio0_reg(31 downto 29); --- gpio0_out(23 downto 0) <= gpio0_reg(23 downto 0); - - enable_misc <= '1' when cpu_address(30 downto 28) = "010" else '0'; - enable_uart <= '1' when enable_misc = '1' and cpu_address(7 downto 4) = "0000" else '0'; - enable_uart_read <= enable_uart and not write_enable; - enable_uart_write <= enable_uart and write_enable; - cpu_address(1 downto 0) <= "00"; - +--%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +-- PROCESSOR +--%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% u1_cpu: mlite_cpu generic map (memory_type => memory_type) PORT MAP ( @@ -121,45 +89,35 @@ begin --architecture data_r => cpu_data_r, mem_pause => cpu_pause); - opt_cache: if use_cache = '0' generate - cache_check <= '0'; - cache_checking <= '0'; - cache_miss <= '0'; - end generate; - - opt_cache2: if use_cache = '1' generate - --Control 4KB unified cache that uses the upper 4KB of the 8KB - --internal RAM. Only lowest 2MB of DDR is cached. - u_cache: cache - generic map (memory_type => memory_type) - PORT MAP ( - clk => clk, - reset => reset, - address_next => address_next, - byte_we_next => byte_we_next, - cpu_address => cpu_address(31 downto 2), - mem_busy => mem_busy, +--%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +-- ADDRESS DECODER +--%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% + write_enable <= '1' when cpu_byte_we /= "0000" else '0'; + mem_busy <= mem_pause_in; + cpu_pause <= '0'; --(uart_write_busy and enable_uart and write_enable) or --UART busy +-- (cpu_address(28) and mem_busy); --DDR or flash + + enable_uart <= '1' when cpu_address(30 downto 28) = "010" and cpu_address(7 downto 4) = "0000" else '0'; + enable_uart_read <= enable_uart and not write_enable; + enable_uart_write <= enable_uart and write_enable; + cpu_address(1 downto 0) <= "00"; + ram_enable <= '1' when address_next(30 downto 28) = "000" else '0'; + ram_byte_we <= byte_we_next; + ram_address(31 downto 13) <= ZERO(31 downto 13); + ram_address(12 downto 2) <= (address_next(12)) & address_next(11 downto 2); + ram_data_w <= cpu_data_w; - cache_check => cache_check, --Stage1: address_next in first 2MB DDR - cache_checking => cache_checking, --Stage2 - cache_miss => cache_miss); --Stage3 - end generate; --opt_cache2 misc_proc: process(clk, reset, cpu_address, enable_misc, ram_data_r, data_read, data_read_uart, cpu_pause, - irq_mask_reg, irq_status, gpio0_reg, write_enable, - cache_checking, - gpioA_in, counter_reg, cpu_data_w) + irq_mask_reg, irq_status, write_enable, + cpu_data_w) begin case cpu_address(30 downto 28) is when "000" => --internal RAM cpu_data_r <= ram_data_r; when "001" => --external RAM - if cache_checking = '1' then - cpu_data_r <= ram_data_r; --cache - else cpu_data_r <= data_read; --DDR - end if; when "010" => --misc case cpu_address(6 downto 4) is when "000" => --uart @@ -168,48 +126,15 @@ begin --architecture cpu_data_r <= ZERO(31 downto 8) & irq_mask_reg; when "010" => --irq_status cpu_data_r <= ZERO(31 downto 8) & irq_status; - when "011" => --gpio0 - cpu_data_r <= gpio0_reg; - when "101" => --gpioA - cpu_data_r <= gpioA_in; - when "110" => --counter - cpu_data_r <= counter_reg; when others => - cpu_data_r <= gpioA_in; + cpu_data_r <= ZERO(31 downto 8) & data_read_uart; end case; when "011" => --flash cpu_data_r <= data_read; when others => cpu_data_r <= ZERO; end case; - - if reset = '1' then - irq_mask_reg <= ZERO(7 downto 0); - gpio0_reg <= ZERO; - counter_reg <= ZERO; - elsif rising_edge(clk) then - if cpu_pause = '0' then - if enable_misc = '1' and write_enable = '1' then - if cpu_address(6 downto 4) = "001" then - irq_mask_reg <= cpu_data_w(7 downto 0); - elsif cpu_address(6 downto 4) = "011" then - gpio0_reg <= gpio0_reg or cpu_data_w; - elsif cpu_address(6 downto 4) = "100" then - gpio0_reg <= gpio0_reg and not cpu_data_w; - end if; - end if; - end if; - counter_reg <= bv_inc(counter_reg); - end if; - end process; - - ram_enable <= '1' when address_next(30 downto 28) = "000" or cache_check = '1' or cache_miss = '1' else '0'; - ram_byte_we <= byte_we_next when cache_miss = '0' else "1111"; - ram_address(31 downto 13) <= ZERO(31 downto 13); - ram_address(12 downto 2) <= (address_next(12) or cache_check) & address_next(11 downto 2) - when cache_miss = '0' else - '1' & cpu_address(11 downto 2); --Update cache after cache miss - ram_data_w <= cpu_data_w when cache_miss = '0' else data_read; + end process; u2_ram: ram generic map (memory_type => memory_type) @@ -235,10 +160,6 @@ begin --architecture busy_write => uart_write_busy, data_avail => uart_data_avail); - address <= cpu_address(31 downto 2); - byte_we <= cpu_byte_we; - data_write <= cpu_data_w; - gpio0_out(28 downto 24) <= ZERO(28 downto 24); end; --architecture logic diff --git a/plasma/logic/ram_image.vhd b/plasma/logic/ram_image.vhd index fe67c8f..c4f51a3 100644 --- a/plasma/logic/ram_image.vhd +++ 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