Adding Hello World Example Runing from Internal SRAM and NAND

Examples/hello_sram/build/.gitignore

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+.svn
+CVS
+*.o
+*.orig
+*.rej
+*.bak
+*.d
+*.bin
+*.dump
+jz_xloader
+
+
+
+
+
+

Examples/hello_sram/build/1

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+
+OBJS	:= start.o main.o jz_serial.o
+
+CROSS	:= mipsel-elf-
+
+CFLAGS	:= -O2 -G 0 -mno-abicalls -fno-pic -mips32 -Iinclude
+AFLAGS	= -D__ASSEMBLY__ $(CFLAGS)
+LDFLAGS	:= -T ld.script -nostdlib -EL
+
+.c.o:
+	$(CROSS)gcc $(CFLAGS) -c $< -o $@
+.S.o:
+	$(CROSS)gcc $(AFLAGS) -c $< -o $@
+
+jz_xloader.bin: jz_xloader
+	$(CROSS)objdump -D jz_xloader $< > jz_xloader.dump
+	$(CROSS)objcopy -O binary $< $@
+
+jz_xloader: $(OBJS)
+	$(CROSS)ld $(LDFLAGS) $^ -o $@
+
+upload: 
+	usbtool 1 
+clean:
+	rm -fr *.o jz_xloader jz_xloader.bin jz_xloader.dump

Examples/hello_sram/build/Makefile

@@ -0,0 +1,26 @@
+
+OBJS	:= start.o main.o jz_serial.o
+
+CROSS	:= mipsel-elf-
+
+CFLAGS	:= -O2 -G 0 -mno-abicalls -fno-pic -mips32 -Iinclude
+AFLAGS	= -D__ASSEMBLY__ $(CFLAGS)
+LDFLAGS	:= -T ld.script -nostdlib -EL
+
+.c.o:
+	$(CROSS)gcc $(CFLAGS) -c $< -o $@
+.S.o:
+	$(CROSS)gcc $(AFLAGS) -c $< -o $@
+
+jz_xloader.bin: jz_xloader
+	$(CROSS)objdump -D jz_xloader $< > jz_xloader.dump
+	$(CROSS)objcopy -O binary $< $@
+
+jz_xloader: $(OBJS)
+	$(CROSS)ld $(LDFLAGS) $^ -o $@
+
+upload: jz_xloader
+	sudo usbtool 1 jz_xloader.bin 0x80000000
+
+clean:
+	rm -fr *.o jz_xloader jz_xloader.bin jz_xloader.dump

Examples/hello_sram/build/include/board.h

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+/*
+ * Copyright (c) 2009, yajin <yajin@vm-kernel.org>
+ * Copyright (c) 2005-2008 Ingenic Semiconductor Inc.
+ *
+ */
+#ifndef __BOARD_H__
+#define __BOARD_H__
+
+
+/*
+  * Define the parameter of your PMP information here.
+  *
+  * ONDA 747: SDRAM:HY57V641620F
+  *                  EXTAL OSC: Great 12M
+  */
+
+/*
+ * Frequency of the external OSC in Hz.
+ */
+#define CFG_EXTAL		12000000
+
+/*
+ * CPU speed.
+ */
+#define CFG_CPU_SPEED		336000000
+
+/*
+ * Serial console.
+ */
+#define CFG_UART_BASE		UART0_BASE
+
+#define CONFIG_BAUDRATE		57600
+
+/*
+ * SDRAM info.
+ */
+ 
+// SDRAM paramters
+#define CFG_SDRAM_BW16		0	/* Data bus width: 0-32bit, 1-16bit */
+#define CFG_SDRAM_BANK4		1	/* Banks each chip: 0-2bank, 1-4bank */
+#define CFG_SDRAM_ROW		12	/* Row address: 11 to 13 */
+#define CFG_SDRAM_COL		8	/* Column address: 8 to 12 */
+#define CFG_SDRAM_CASL		2	/* CAS latency: 2 or 3 */
+
+// SDRAM Timings, unit: ns
+#define CFG_SDRAM_TRAS		45	/* RAS# Active Time */
+#define CFG_SDRAM_RCD		20	/* RAS# to CAS# Delay */
+#define CFG_SDRAM_TPC		20	/* RAS# Precharge Time */
+#define CFG_SDRAM_TRWL		7	/* Write Latency Time */
+#define CFG_SDRAM_TREF		7812	/* Refresh period: 8192 refresh cycles/64ms */
+
+
+#endif

Examples/hello_sram/build/include/types.h

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+/*
+  * Copyright (c) 2009, yajin <yajin@vm-kernel.org>
+  *
+  * This program is free software; you can redistribute it and/or
+  * modify it under the terms of the GNU General Public License as
+  * published by the Free Software Foundation; either version 2 of
+  * the License, or (at your option) any later version.
+  */
+
+#ifndef __TYPES_H__
+#define __TYPES_H__
+
+#define u32 unsigned int
+#define u16 unsigned short
+#define u8 unsigned char
+
+#endif /* __TYPES_H__ */

Examples/hello_sram/build/jz_serial.c

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+/*
+ * Jz47xx UART support
+ *
+ * Options hardcoded to 8N1
+ *
+ *  Copyright (c) 2009, yajin <yajin@vm-kernel.org>
+ *  Copyright (c) 2005 - 2008, Ingenic Semiconductor Inc.
+ *  Ingenic Semiconductor, <jlwei@ingenic.cn>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <jz4740.h>
+#include <board.h>
+
+#undef UART_BASE
+#ifndef CFG_UART_BASE
+#define UART_BASE  UART0_BASE
+#else
+#define UART_BASE  CFG_UART_BASE
+#endif
+
+/******************************************************************************
+*
+* serial_init - initialize a channel
+*
+* This routine initializes the number of data bits, parity
+* and set the selected baud rate. Interrupts are disabled.
+* Set the modem control signals if the option is selected.
+*
+* RETURNS: N/A
+*/
+
+static void serial_setbrg(void)
+{
+    volatile u8 *uart_lcr = (volatile u8 *) (UART_BASE + OFF_LCR);
+    volatile u8 *uart_dlhr = (volatile u8 *) (UART_BASE + OFF_DLHR);
+    volatile u8 *uart_dllr = (volatile u8 *) (UART_BASE + OFF_DLLR);
+    u32 baud_div, tmp;
+
+    baud_div = CFG_EXTAL / 16 / CONFIG_BAUDRATE;
+    tmp = *uart_lcr;
+    tmp |= UART_LCR_DLAB;
+    *uart_lcr = tmp;
+
+    *uart_dlhr = (baud_div >> 8) & 0xff;
+    *uart_dllr = baud_div & 0xff;
+
+    tmp &= ~UART_LCR_DLAB;
+    *uart_lcr = tmp;
+}
+
+int serial_init(void)
+{
+    volatile u8 *uart_fcr = (volatile u8 *) (UART_BASE + OFF_FCR);
+    volatile u8 *uart_lcr = (volatile u8 *) (UART_BASE + OFF_LCR);
+    volatile u8 *uart_ier = (volatile u8 *) (UART_BASE + OFF_IER);
+    volatile u8 *uart_sircr = (volatile u8 *) (UART_BASE + OFF_SIRCR);
+
+    /* Disable port interrupts while changing hardware */
+    *uart_ier = 0;
+
+    /* Disable UART unit function */
+    *uart_fcr = ~UART_FCR_UUE;
+
+    /* Set both receiver and transmitter in UART mode (not SIR) */
+    *uart_sircr = ~(SIRCR_RSIRE | SIRCR_TSIRE);
+
+    /* Set databits, stopbits and parity. (8-bit data, 1 stopbit, no parity) */
+    *uart_lcr = UART_LCR_WLEN_8 | UART_LCR_STOP_1;
+
+    /* Set baud rate */
+    serial_setbrg();
+
+    /* Enable UART unit, enable and clear FIFO */
+    *uart_fcr = UART_FCR_UUE | UART_FCR_FE | UART_FCR_TFLS | UART_FCR_RFLS;
+
+    return 0;
+}
+
+void serial_putc(const char c)
+{
+    volatile u8 *uart_lsr = (volatile u8 *) (UART_BASE + OFF_LSR);
+    volatile u8 *uart_tdr = (volatile u8 *) (UART_BASE + OFF_TDR);
+
+    if (c == '\n')
+        serial_putc('\r');
+
+    /* Wait for fifo to shift out some bytes */
+    while (!((*uart_lsr & (UART_LSR_TDRQ | UART_LSR_TEMT)) == 0x60));
+
+    *uart_tdr = (u8) c;
+}
+
+void serial_puts(const char *s)
+{
+    while (*s)
+    {
+        serial_putc(*s++);
+    }
+}

Examples/hello_sram/build/ld.script

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+OUTPUT_ARCH(mips)
+ENTRY(startup)
+MEMORY
+{
+	ram	: ORIGIN = 0x80000000 , LENGTH = 0x100000
+}
+
+SECTIONS
+{
+	. = ALIGN(4);
+	.text : { *(.text*) } > ram
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata*) } > ram
+
+	. = ALIGN(4);
+	.sdata : { *(.sdata*) } > ram
+
+	. = ALIGN(4);
+	.data : { *(.data*) *(.scommon*) *(.reginfo*) } > ram
+
+	_gp = ALIGN(16);
+	.got : { *(.got*) } > ram
+
+	. = ALIGN(4);
+	.sbss : { *(.sbss*) } > ram
+	.bss : { *(.bss*) } > ram
+	. = ALIGN (4);
+}

Examples/hello_sram/build/main.c

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+/*
+  * Copyright (c) 2009, yajin <yajin@vm-kernel.org>
+  * Copyright (c) 2005-2008  Ingenic Semiconductor Inc.
+  * Author: <jlwei@ingenic.cn>
+  *
+  * This program is free software; you can redistribute it and/or
+  * modify it under the terms of the GNU General Public License as
+  * published by the Free Software Foundation; either version 2 of
+  * the License, or (at your option) any later version.
+  */
+
+
+
+#include <jz4740.h>
+#include <board.h>
+
+#define VERSION "0.01"
+
+static void gpio_init(void)
+{
+    __gpio_as_sdram_32bit();
+    __gpio_as_uart0();
+    __gpio_as_nand();
+}
+
+static void nand_enable()
+{
+    REG_EMC_NFCSR |= EMC_NFCSR_NFE1;
+    REG_EMC_SMCR1 = 0x04444400;
+}
+
+/* PLL output clock = EXTAL * NF / (NR * NO)
+ *
+ * NF = FD + 2, NR = RD + 2
+ * NO = 1 (if OD = 0), NO = 2 (if OD = 1 or 2), NO = 4 (if OD = 3)
+ */
+static void pll_init(void)
+{
+    register unsigned int cfcr, plcr1;
+    int n2FR[33] = {
+        0, 0, 1, 2, 3, 0, 4, 0, 5, 0, 0, 0, 6, 0, 0, 0,
+        7, 0, 0, 0, 0, 0, 0, 0, 8, 0, 0, 0, 0, 0, 0, 0,
+        9
+    };
+    int div[5] = { 0, 3, 3, 3, 3 };     /* divisors of I:S:P:M:L */
+    int nf, pllout2;
+
+    cfcr = CPM_CPCCR_CLKOEN |
+        (n2FR[div[0]] << CPM_CPCCR_CDIV_BIT) |
+        (n2FR[div[1]] << CPM_CPCCR_HDIV_BIT) |
+        (n2FR[div[2]] << CPM_CPCCR_PDIV_BIT) |
+        (n2FR[div[3]] << CPM_CPCCR_MDIV_BIT) |
+        (n2FR[div[4]] << CPM_CPCCR_LDIV_BIT);
+
+    pllout2 = (cfcr & CPM_CPCCR_PCS) ? CFG_CPU_SPEED : (CFG_CPU_SPEED / 2);
+
+    /* Init USB Host clock, pllout2 must be n*48MHz */
+    REG_CPM_UHCCDR = pllout2 / 48000000 - 1;
+
+    nf = CFG_CPU_SPEED * 2 / CFG_EXTAL;
+    plcr1 = ((nf + 2) << CPM_CPPCR_PLLM_BIT) |  /* FD */
+        (0 << CPM_CPPCR_PLLN_BIT) |     /* RD=0, NR=2 */
+        (0 << CPM_CPPCR_PLLOD_BIT) |    /* OD=0, NO=1 */
+        (0x20 << CPM_CPPCR_PLLST_BIT) | /* PLL stable time */
+        CPM_CPPCR_PLLEN;        /* enable PLL */
+
+    /* init PLL */
+    REG_CPM_CPCCR = cfcr;
+    REG_CPM_CPPCR = plcr1;
+
+}
+
+/*
+ * Init SDRAM memory.
+ */
+
+static void sdram_init(void)
+{
+    register unsigned int dmcr0, dmcr, sdmode, tmp, cpu_clk, mem_clk, ns;
+
+    unsigned int cas_latency_sdmr[2] = {
+        EMC_SDMR_CAS_2,
+        EMC_SDMR_CAS_3,
+    };
+
+    unsigned int cas_latency_dmcr[2] = {
+        1 << EMC_DMCR_TCL_BIT,  /* CAS latency is 2 */
+        2 << EMC_DMCR_TCL_BIT   /* CAS latency is 3 */
+    };
+
+    int div[] = { 1, 2, 3, 4, 6, 8, 12, 16, 24, 32 };
+
+    cpu_clk = CFG_CPU_SPEED;
+    mem_clk = cpu_clk * div[__cpm_get_cdiv()] / div[__cpm_get_mdiv()];
+
+    //REG_EMC_BCR = 0;      /* Disable bus release */
+    REG_EMC_RTCSR = 0;          /* Disable clock for counting */
+    REG_EMC_RTCOR = 0;
+    REG_EMC_RTCNT = 0;
+
+    /* Fault DMCR value for mode register setting */
+#define SDRAM_ROW0    11
+#define SDRAM_COL0     8
+#define SDRAM_BANK40   0
+
+    dmcr0 = ((SDRAM_ROW0 - 11) << EMC_DMCR_RA_BIT) |
+        ((SDRAM_COL0 - 8) << EMC_DMCR_CA_BIT) |
+        (SDRAM_BANK40 << EMC_DMCR_BA_BIT) |
+        (CFG_SDRAM_BW16 << EMC_DMCR_BW_BIT) |
+        EMC_DMCR_EPIN | cas_latency_dmcr[((CFG_SDRAM_CASL == 3) ? 1 : 0)];
+
+    /* Basic DMCR value */
+    dmcr = ((CFG_SDRAM_ROW - 11) << EMC_DMCR_RA_BIT) |
+        ((CFG_SDRAM_COL - 8) << EMC_DMCR_CA_BIT) |
+        (CFG_SDRAM_BANK4 << EMC_DMCR_BA_BIT) |
+        (CFG_SDRAM_BW16 << EMC_DMCR_BW_BIT) |
+        EMC_DMCR_EPIN | cas_latency_dmcr[((CFG_SDRAM_CASL == 3) ? 1 : 0)];
+
+    /* SDRAM timimg */
+    ns = 1000000000 / mem_clk;
+    tmp = CFG_SDRAM_TRAS / ns;
+    if (tmp < 4)
+        tmp = 4;
+    if (tmp > 11)
+        tmp = 11;
+    dmcr |= ((tmp - 4) << EMC_DMCR_TRAS_BIT);
+    tmp = CFG_SDRAM_RCD / ns;
+    if (tmp > 3)
+        tmp = 3;
+    dmcr |= (tmp << EMC_DMCR_RCD_BIT);
+    tmp = CFG_SDRAM_TPC / ns;
+    if (tmp > 7)
+        tmp = 7;
+    dmcr |= (tmp << EMC_DMCR_TPC_BIT);
+    tmp = CFG_SDRAM_TRWL / ns;
+    if (tmp > 3)
+        tmp = 3;
+    dmcr |= (tmp << EMC_DMCR_TRWL_BIT);
+    tmp = (CFG_SDRAM_TRAS + CFG_SDRAM_TPC) / ns;
+    if (tmp > 14)
+        tmp = 14;
+    dmcr |= (((tmp + 1) >> 1) << EMC_DMCR_TRC_BIT);
+
+    /* SDRAM mode value */
+    sdmode = EMC_SDMR_BT_SEQ |
+        EMC_SDMR_OM_NORMAL |
+        EMC_SDMR_BL_4 | cas_latency_sdmr[((CFG_SDRAM_CASL == 3) ? 1 : 0)];
+
+    /* Stage 1. Precharge all banks by writing SDMR with DMCR.MRSET=0 */
+    REG_EMC_DMCR = dmcr;
+    REG8(EMC_SDMR0 | sdmode) = 0;
+
+    /* Wait for precharge, > 200us */
+    tmp = (cpu_clk / 1000000) * 1000;
+    while (tmp--);
+
+    /* Stage 2. Enable auto-refresh */
+    REG_EMC_DMCR = dmcr | EMC_DMCR_RFSH;
+
+    tmp = CFG_SDRAM_TREF / ns;
+    tmp = tmp / 64 + 1;
+    if (tmp > 0xff)
+        tmp = 0xff;
+    REG_EMC_RTCOR = tmp;
+    REG_EMC_RTCNT = 0;
+    REG_EMC_RTCSR = EMC_RTCSR_CKS_64;   /* Divisor is 64, CKO/64 */
+
+    /* Wait for number of auto-refresh cycles */
+    tmp = (cpu_clk / 1000000) * 1000;
+    while (tmp--);
+
+    /* Stage 3. Mode Register Set */
+    REG_EMC_DMCR = dmcr0 | EMC_DMCR_RFSH | EMC_DMCR_MRSET;
+    REG8(EMC_SDMR0 | sdmode) = 0;
+
+    /* Set back to basic DMCR value */
+    REG_EMC_DMCR = dmcr | EMC_DMCR_RFSH | EMC_DMCR_MRSET;
+
+    /* everything is ok now */
+}
+
+void main_func(void)
+{
+
+    /*
+     * Init gpio, serial, pll and sdram
+     */
+    gpio_init();
+    serial_init();
+    serial_puts("\nJZ x_loader version " VERSION "\n");
+    serial_puts("Copyright 2009 by yajin<yajin@vm-kernel.org>\n");
+    pll_init();
+    sdram_init();
+}

Examples/hello_sram/build/start.S

@@ -0,0 +1,43 @@
+/*
+ * Copyright (c) 2009, yajin <yajin@vm-kernel.org>
+ * Copyright (c) 2005-2008  Ingenic Semiconductor Inc.
+ * Author: <jlwei@ingenic.cn>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+#include <jz4740.h>
+#include <board.h>
+
+	.text
+	.set noreorder
+	.global startup
+startup:
+	/*
+	 * Disable all interrupts
+	 */
+	la	$8, 0xB0001004		/* INTC_IMR */
+	li	$9, 0xffffffff
+	sw	$9, 0($8)
+
+	/* 
+	 * CU0=UM=EXL=IE=0, BEV=ERL=1, IP2~7=1
+	 */
+	li	$26, 0x0040FC04
+	mtc0	$26, $12		/* CP0_STATUS */
+
+	/* IV=1, use the specical interrupt vector (0x200) */
+	li	$26, 0x00800000
+	mtc0	$26, $13		/* CP0_CAUSE */
+
+	/* Setup stack pointer */
+	la	$29, 0x81000000
+
+	/* Jump to the main routine */
+	j	main_func
+	nop
+	.set reorder
+