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Changing D10, D9, D8 footprints to 0805 Adding DC jack polarity indication

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This commit is contained in:
Carlos Camargo
2010-07-30 10:46:16 -05:00
parent 7a1761c8cb
commit f95025de7c
17 changed files with 47428 additions and 47446 deletions
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4
Examples/ADC/logic/ADC.ucf
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@@ -2,6 +2,10 @@ NET clk LOC = "P38";
NET reset LOC = "P30"; #WARNING change to another pin
NET led LOC = "P44";
NET irq_pin LOC = "P71";
NET OD1 LOC = "P68";
NET OD2 LOC = "P66";
NET OD3 LOC = "P63";
#ADDRESS BUS
NET "addr<12>" LOC = "P90";

10
Examples/ADC/logic/ADC.v
View File

@@ -1,18 +1,20 @@
`timescale 1ns / 1ps
module ADC(clk, sram_data, addr, nwe, ncs, noe, reset, led, ADC_EOC,
ADC_SCLK, ADC_SDIN, ADC_SDOUT, ADC_CS, ADC_CSTART, irq_pin);
ADC_SCLK, ADC_SDIN, ADC_SDOUT, ADC_CS, ADC_CSTART, irq_pin, OD1, OD2, OD3);
parameter B = (7);
input clk, addr, nwe, ncs, noe, reset, ADC_EOC;
inout [B:0] sram_data;
output led, ADC_CS, ADC_CSTART, ADC_SCLK;
output OD1, OD2, OD3;
inout ADC_SDIN, ADC_SDOUT;
input irq_pin;
// Internal conection
reg led;
reg OD1, OD2, OD3;
// synchronize signals
reg sncs, snwe;
@@ -37,7 +39,11 @@ module ADC(clk, sram_data, addr, nwe, ncs, noe, reset, led, ADC_EOC,
counter <= {25{1'b0}};
else
counter <= counter + 1;
led <=counter[25];
led <= counter[25];
OD1 <= counter[25];
OD2 <= counter[16];
OD3 <= counter[15];
end
// interefaz signals assignments