diff --git a/plasma/logic/plasma_TB.v b/plasma/logic/plasma_TB.v
new file mode 100644
index 0000000..c92be26
--- /dev/null
+++ b/plasma/logic/plasma_TB.v
@@ -0,0 +1,58 @@
+`timescale 1ns / 1ps
+
+module plasma_TB_v;
+
+   reg clk;
+   reg reset;
+
+
+   plasma uut( .clk(clk), .reset(reset));
+
+
+   parameter PERIOD  = 20;
+   parameter real DUTY_CYCLE = 0.5;
+   parameter OFFSET  = 0;
+   parameter TSET    = 3;
+   parameter THLD    = 3;
+   parameter NWS     = 3;
+   parameter CAM_OFF = 4000;
+	 
+	 reg [15:0] data_tx;	 
+
+
+	event reset_trigger;
+	event reset_done_trigger;
+
+    initial begin // Reset the system, Start the image capture process
+      forever begin 
+        @ (reset_trigger);
+        @ (negedge clk);
+        reset = 1;
+        @ (negedge clk);
+        reset = 0;
+        -> reset_done_trigger;
+      end
+    end
+
+	 
+    initial begin  // Initialize Inputs
+      clk = 0;
+    end
+
+   initial  begin  // Process for clk
+     #OFFSET;
+     forever
+     begin
+       clk = 1'b0;
+       #(PERIOD-(PERIOD*DUTY_CYCLE)) clk = 1'b1;
+       #(PERIOD*DUTY_CYCLE);
+     end
+   end
+
+ initial begin: TEST_CASE	
+     #10 -> reset_trigger;
+     @ (reset_done_trigger); 
+     // Write data to SRAM
+ end
+endmodule
+
diff --git a/plasma/logic/plasma_TB.vhd b/plasma/logic/plasma_TB.vhd
new file mode 100644
index 0000000..435236f
--- /dev/null
+++ b/plasma/logic/plasma_TB.vhd
@@ -0,0 +1,64 @@
+---------------------------------------------------------------------
+-- TITLE: Test Bench
+-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
+-- DATE CREATED: 4/21/01
+-- FILENAME: tbench.vhd
+-- PROJECT: Plasma CPU core
+-- COPYRIGHT: Software placed into the public domain by the author.
+--    Software 'as is' without warranty.  Author liable for nothing.
+-- DESCRIPTION:
+--    This entity provides a test bench for testing the Plasma CPU core.
+---------------------------------------------------------------------
+library ieee;
+use ieee.std_logic_1164.all;
+use work.mlite_pack.all;
+use ieee.std_logic_unsigned.all;
+
+entity tbench is
+end; --entity tbench
+
+architecture logic of tbench is
+   constant memory_type : string := 
+   "TRI_PORT_X";   
+--   "DUAL_PORT_";
+--   "ALTERA_LPM";
+--   "XILINX_16X";
+
+   constant log_file  : string := 
+--   "UNUSED";
+   "output.txt";
+
+   signal clk         : std_logic := '1';
+   signal reset       : std_logic := '1';
+   signal interrupt   : std_logic := '0';
+   signal mem_write   : std_logic;
+   signal address     : std_logic_vector(31 downto 2);
+   signal data_write  : std_logic_vector(31 downto 0);
+   signal data_read   : std_logic_vector(31 downto 0);
+   signal pause1      : std_logic := '0';
+   signal pause2      : std_logic := '0';
+   signal pause       : std_logic;
+   signal byte_we     : std_logic_vector(3 downto 0);
+   signal uart_write  : std_logic;
+   signal gpioA_in    : std_logic_vector(31 downto 0) := (others => '0');
+begin  --architecture
+   --Uncomment the line below to test interrupts
+   --interrupt <= '1' after 20 us when interrupt = '0' else '0' after 445 ns;
+
+   clk   <= not clk after 50 ns;
+   reset <= '0' after 500 ns;
+   pause <= '0';
+
+   u1_plasma: plasma
+      generic map (memory_type => memory_type,
+                   log_file    => log_file)
+      PORT MAP (
+         clk               => clk,
+         reset             => reset,
+         uart_read         => uart_write,
+         uart_write        => uart_write,
+         data_read         => data_read,
+         mem_pause_in      => pause
+     );
+
+end; --architecture logic