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Release 10.1.03 Trace  (lin)
Copyright (c) 1995-2008 Xilinx, Inc.  All rights reserved.

/opt/cad/Xilinx/10.1/ISE/bin/lin/unwrapped/trce -v 25 project_r.ncd project.pcf

Design file:              project_r.ncd
Physical constraint file: project.pcf
Device,package,speed:     xc3s500e,vq100,-4 (PRODUCTION 1.27 2008-01-09)
Report level:             verbose report, limited to 25 items per constraint

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
--------------------------------------------------------------------------------

INFO:Timing:2698 - No timing constraints found, doing default enumeration.
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths 
   option. All paths that are not constrained will be reported in the 
   unconstrained paths section(s) of the report.
INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on 
   a 50 Ohm transmission line loading model.  For the details of this model, 
   and for more information on accounting for different loading conditions, 
   please see the device datasheet.



Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Setup/Hold to clock clk
------------+------------+------------+------------------+--------+
            |  Setup to  |  Hold to   |                  | Clock  |
Source      | clk (edge) | clk (edge) |Internal Clock(s) | Phase  |
------------+------------+------------+------------------+--------+
RxD         |    4.665(R)|   -0.791(R)|clk_BUFGP         |   0.000|
addr<0>     |    4.669(F)|   -0.795(F)|clk_BUFGP         |   0.000|
addr<1>     |    4.669(F)|   -0.795(F)|clk_BUFGP         |   0.000|
addr<2>     |    4.652(F)|   -0.775(F)|clk_BUFGP         |   0.000|
ncs         |    4.667(F)|   -0.792(F)|clk_BUFGP         |   0.000|
nwe         |    4.666(F)|   -0.791(F)|clk_BUFGP         |   0.000|
reset       |    4.649(R)|   -0.365(R)|clk_BUFGP         |   0.000|
sram_data<0>|    4.664(F)|   -0.789(F)|clk_BUFGP         |   0.000|
sram_data<1>|    4.664(F)|   -0.789(F)|clk_BUFGP         |   0.000|
sram_data<2>|    4.664(F)|   -0.789(F)|clk_BUFGP         |   0.000|
sram_data<3>|    4.664(F)|   -0.789(F)|clk_BUFGP         |   0.000|
sram_data<4>|    4.667(F)|   -0.792(F)|clk_BUFGP         |   0.000|
sram_data<5>|    4.667(F)|   -0.792(F)|clk_BUFGP         |   0.000|
sram_data<6>|    4.651(F)|   -0.774(F)|clk_BUFGP         |   0.000|
sram_data<7>|    4.651(F)|   -0.774(F)|clk_BUFGP         |   0.000|
------------+------------+------------+------------------+--------+

Clock clk to Pad
------------+------------+------------------+--------+
            | clk (edge) |                  | Clock  |
Destination |   to PAD   |Internal Clock(s) | Phase  |
------------+------------+------------------+--------+
TxD         |    6.163(R)|clk_BUFGP         |   0.000|
irq_pin     |   10.697(R)|clk_BUFGP         |   0.000|
led         |    6.155(R)|clk_BUFGP         |   0.000|
sram_data<0>|   14.532(R)|clk_BUFGP         |   0.000|
            |   16.364(F)|clk_BUFGP         |   0.000|
sram_data<1>|   15.462(R)|clk_BUFGP         |   0.000|
            |   17.685(F)|clk_BUFGP         |   0.000|
sram_data<2>|   15.054(R)|clk_BUFGP         |   0.000|
            |   16.594(F)|clk_BUFGP         |   0.000|
sram_data<3>|   14.794(R)|clk_BUFGP         |   0.000|
            |   16.334(F)|clk_BUFGP         |   0.000|
sram_data<4>|   14.119(R)|clk_BUFGP         |   0.000|
            |   15.659(F)|clk_BUFGP         |   0.000|
sram_data<5>|   15.051(R)|clk_BUFGP         |   0.000|
            |   16.591(F)|clk_BUFGP         |   0.000|
sram_data<6>|   15.120(R)|clk_BUFGP         |   0.000|
            |   16.660(F)|clk_BUFGP         |   0.000|
sram_data<7>|   14.331(R)|clk_BUFGP         |   0.000|
            |   17.406(F)|clk_BUFGP         |   0.000|
------------+------------+------------------+--------+

Clock to Setup on destination clock clk
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clk            |    9.370|    7.997|         |         |
---------------+---------+---------+---------+---------+

Pad to Pad
---------------+---------------+---------+
Source Pad     |Destination Pad|  Delay  |
---------------+---------------+---------+
ncs            |sram_data<0>   |    8.998|
ncs            |sram_data<1>   |    9.262|
ncs            |sram_data<2>   |    8.918|
ncs            |sram_data<3>   |    9.517|
ncs            |sram_data<4>   |    9.167|
ncs            |sram_data<5>   |    8.636|
ncs            |sram_data<6>   |    9.866|
ncs            |sram_data<7>   |    9.858|
noe            |sram_data<0>   |    8.802|
noe            |sram_data<1>   |    9.066|
noe            |sram_data<2>   |    8.722|
noe            |sram_data<3>   |    9.321|
noe            |sram_data<4>   |    8.971|
noe            |sram_data<5>   |    8.440|
noe            |sram_data<6>   |    9.670|
noe            |sram_data<7>   |    9.662|
---------------+---------------+---------+


Analysis completed Thu Nov 11 14:39:04 2010 
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Trace Settings:
-------------------------
Trace Settings 

Peak Memory Usage: 93 MB