]> Release 10.1.03 Trace (lin)Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved./opt/cad/Xilinx/10.1/ISE/bin/lin/unwrapped/trce -v 25 project_r.ncd project.pcf project_r.ncdproject.pcfxc3s500e-4PRODUCTION 1.27 2008-01-0925INFO:Timing:2698 - No timing constraints found, doing default enumeration.INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report.INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model. For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet.clkRxD4.665-0.791addr<0>4.669-0.795addr<1>4.669-0.795addr<2>4.652-0.775ncs4.667-0.792nwe4.666-0.791reset4.649-0.365sram_data<0>4.664-0.789sram_data<1>4.664-0.789sram_data<2>4.664-0.789sram_data<3>4.664-0.789sram_data<4>4.667-0.792sram_data<5>4.667-0.792sram_data<6>4.651-0.774sram_data<7>4.651-0.774clkclkclk9.3707.997ncssram_data<0>8.998ncssram_data<1>9.262ncssram_data<2>8.918ncssram_data<3>9.517ncssram_data<4>9.167ncssram_data<5>8.636ncssram_data<6>9.866ncssram_data<7>9.858noesram_data<0>8.802noesram_data<1>9.066noesram_data<2>8.722noesram_data<3>9.321noesram_data<4>8.971noesram_data<5>8.440noesram_data<6>9.670noesram_data<7>9.662Thu Nov 11 14:39:04 2010 TraceTrace Settings Peak Memory Usage: 93 MB