# //  ModelSim SE 6.0d Apr 25 2005 Linux 2.6.32-21-generic
# //
# //  Copyright Mentor Graphics Corporation 2005
# //              All Rights Reserved.
# //
# //  THIS WORK CONTAINS TRADE SECRET AND 
# //  PROPRIETARY INFORMATION WHICH IS THE PROPERTY
# //  OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS
# //  AND IS SUBJECT TO LICENSE TERMS.
# //
# do plasma_3e_TB.do 
# Reading /home/opt/cad/modeltech/linux/../modelsim.ini
# "work" maps to directory work. (Default mapping)
# Model Technology ModelSim SE vcom 6.0d Compiler 2005.04 Apr 25 2005
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Compiling package mlite_pack
# -- Compiling package body mlite_pack
# -- Loading package mlite_pack
# Model Technology ModelSim SE vcom 6.0d Compiler 2005.04 Apr 25 2005
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package mlite_pack
# -- Compiling entity plasma
# -- Compiling architecture logic of plasma
# Model Technology ModelSim SE vcom 6.0d Compiler 2005.04 Apr 25 2005
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package mlite_pack
# -- Compiling entity alu
# -- Compiling architecture logic of alu
# Model Technology ModelSim SE vcom 6.0d Compiler 2005.04 Apr 25 2005
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package mlite_pack
# -- Compiling entity control
# -- Compiling architecture logic of control
# Model Technology ModelSim SE vcom 6.0d Compiler 2005.04 Apr 25 2005
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package mlite_pack
# -- Compiling entity mem_ctrl
# -- Compiling architecture logic of mem_ctrl
# Model Technology ModelSim SE vcom 6.0d Compiler 2005.04 Apr 25 2005
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package mlite_pack
# -- Compiling entity mult
# -- Compiling architecture logic of mult
# Model Technology ModelSim SE vcom 6.0d Compiler 2005.04 Apr 25 2005
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package mlite_pack
# -- Compiling entity shifter
# -- Compiling architecture logic of shifter
# Model Technology ModelSim SE vcom 6.0d Compiler 2005.04 Apr 25 2005
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package mlite_pack
# -- Compiling entity bus_mux
# -- Compiling architecture logic of bus_mux
# Model Technology ModelSim SE vcom 6.0d Compiler 2005.04 Apr 25 2005
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package mlite_pack
# -- Compiling entity ddr_ctrl
# -- Compiling architecture logic of ddr_ctrl
# Model Technology ModelSim SE vcom 6.0d Compiler 2005.04 Apr 25 2005
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package mlite_pack
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Compiling entity mlite_cpu
# -- Compiling architecture logic of mlite_cpu
# Model Technology ModelSim SE vcom 6.0d Compiler 2005.04 Apr 25 2005
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package mlite_pack
# -- Compiling entity pc_next
# -- Compiling architecture logic of pc_next
# Model Technology ModelSim SE vcom 6.0d Compiler 2005.04 Apr 25 2005
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package vcomponents
# -- Loading package mlite_pack
# -- Compiling entity cache
# -- Compiling architecture logic of cache
# Model Technology ModelSim SE vcom 6.0d Compiler 2005.04 Apr 25 2005
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package mlite_pack
# -- Compiling entity eth_dma
# -- Compiling architecture logic of eth_dma
# Model Technology ModelSim SE vcom 6.0d Compiler 2005.04 Apr 25 2005
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package mlite_pack
# -- Compiling entity pipeline
# -- Compiling architecture logic of pipeline
# Model Technology ModelSim SE vcom 6.0d Compiler 2005.04 Apr 25 2005
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package mlite_pack
# -- Compiling entity reg_bank
# -- Compiling architecture ram_block of reg_bank
# Model Technology ModelSim SE vcom 6.0d Compiler 2005.04 Apr 25 2005
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package attributes
# -- Loading package std_logic_misc
# -- Loading package std_logic_arith
# -- Loading package textio
# -- Loading package std_logic_textio
# -- Loading package std_logic_unsigned
# -- Loading package mlite_pack
# -- Compiling entity uart
# -- Compiling architecture logic of uart
# Model Technology ModelSim SE vcom 6.0d Compiler 2005.04 Apr 25 2005
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Compiling entity plasma_3e
# -- Compiling architecture logic of plasma_3e
# Model Technology ModelSim SE vcom 6.0d Compiler 2005.04 Apr 25 2005
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package attributes
# -- Loading package std_logic_misc
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package mlite_pack
# -- Loading package vcomponents
# -- Compiling entity ram
# -- Compiling architecture logic of ram
# Model Technology ModelSim SE vcom 6.0d Compiler 2005.04 Apr 25 2005
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package mlite_pack
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Compiling entity tbench
# -- Compiling architecture logic of tbench
# vsim -t 1ps tbench 
# Loading /home/opt/cad/modeltech/linux/../std.standard
# Loading /home/opt/cad/modeltech/linux/../ieee.std_logic_1164(body)
# Loading work.mlite_pack(body)
# Loading /home/opt/cad/modeltech/linux/../ieee.std_logic_arith(body)
# Loading /home/opt/cad/modeltech/linux/../ieee.std_logic_unsigned(body)
# Loading work.tbench(logic)
# Loading work.plasma(logic)
# Loading work.mlite_cpu(logic)
# Loading work.pc_next(logic)
# Loading work.mem_ctrl(logic)
# Loading work.control(logic)
# Loading work.reg_bank(ram_block)
# Loading work.bus_mux(logic)
# Loading work.alu(logic)
# Loading work.shifter(logic)
# Loading work.mult(logic)
# Loading /opt/cad/modeltech/xilinx/vhdl/unisim.vcomponents
# Loading work.cache(logic)
# Loading /home/opt/cad/modeltech/linux/../synopsys.attributes
# Loading /home/opt/cad/modeltech/linux/../ieee.std_logic_misc(body)
# Loading work.ram(logic)
# Loading /home/opt/cad/modeltech/linux/../std.textio(body)
# Loading /home/opt/cad/modeltech/linux/../ieee.vital_timing(body)
# Loading /home/opt/cad/modeltech/linux/../ieee.vital_primitives(body)
# Loading /opt/cad/modeltech/xilinx/vhdl/unisim.vpkg(body)
# Loading /opt/cad/modeltech/xilinx/vhdl/unisim.ramb16_s9(ramb16_s9_v)
# Loading /home/opt/cad/modeltech/linux/../ieee.std_logic_textio(body)
# Loading work.uart(logic)
# Loading work.eth_dma(logic)
# .main_pane.mdi.interior.cs.vm.paneset.cli_0.wf.clip.cs
# .main_pane.workspace
# .main_pane.signals.interior.cs
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
#    Time: 0 ps  Iteration: 0  Instance: /tbench
# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0.
#    Time: 0 ps  Iteration: 0  Instance: /tbench
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
#    Time: 0 ps  Iteration: 0  Instance: /tbench/u1_plasma/dma_gen2/u4_eth
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
#    Time: 0 ps  Iteration: 0  Instance: /tbench/u1_plasma/dma_gen2/u4_eth
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
#    Time: 0 ps  Iteration: 0  Instance: /tbench/u1_plasma/u3_uart
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
#    Time: 0 ps  Iteration: 0  Instance: /tbench/u1_plasma/opt_cache2/u_cache
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
#    Time: 0 ps  Iteration: 0  Instance: /tbench/u1_plasma/opt_cache2/u_cache
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
#    Time: 0 ps  Iteration: 0  Instance: /tbench/u1_plasma/opt_cache2/u_cache
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
#    Time: 0 ps  Iteration: 0  Instance: /tbench/u1_plasma/u1_cpu/u8_mult
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
#    Time: 0 ps  Iteration: 0  Instance: /tbench/u1_plasma/u1_cpu/u8_mult
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
#    Time: 0 ps  Iteration: 0  Instance: /tbench/u1_plasma/u1_cpu/u8_mult
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
#    Time: 0 ps  Iteration: 0  Instance: /tbench/u1_plasma/u1_cpu/u8_mult
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
#    Time: 0 ps  Iteration: 0  Instance: /tbench/u1_plasma/u1_cpu/u8_mult
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
#    Time: 0 ps  Iteration: 0  Instance: /tbench/u1_plasma/u1_cpu/u8_mult
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
#    Time: 0 ps  Iteration: 0  Instance: /tbench/u1_plasma/u1_cpu/u4_reg_bank/tri_port_mem
# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0.
#    Time: 0 ps  Iteration: 0  Instance: /tbench/u1_plasma/u1_cpu/u4_reg_bank/tri_port_mem
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
#    Time: 0 ps  Iteration: 0  Instance: /tbench/u1_plasma/u1_cpu/u4_reg_bank/tri_port_mem
# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0.
#    Time: 0 ps  Iteration: 0  Instance: /tbench/u1_plasma/u1_cpu/u4_reg_bank/tri_port_mem
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
#    Time: 0 ps  Iteration: 0  Instance: /tbench/u1_plasma/u1_cpu/u4_reg_bank
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
#    Time: 0 ps  Iteration: 0  Instance: /tbench/u1_plasma/u1_cpu/u4_reg_bank
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
#    Time: 0 ps  Iteration: 0  Instance: /tbench/u1_plasma/u1_cpu/u4_reg_bank
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
#    Time: 0 ps  Iteration: 0  Instance: /tbench/u1_plasma/u1_cpu/u4_reg_bank
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
#    Time: 0 ps  Iteration: 0  Instance: /tbench/u1_plasma/u1_cpu
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
#    Time: 0 ps  Iteration: 1  Instance: /tbench/u1_plasma/u1_cpu/u4_reg_bank/tri_port_mem
# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0.
#    Time: 0 ps  Iteration: 1  Instance: /tbench/u1_plasma/u1_cpu/u4_reg_bank/tri_port_mem
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
#    Time: 0 ps  Iteration: 1  Instance: /tbench/u1_plasma/u1_cpu/u4_reg_bank/tri_port_mem
# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0.
#    Time: 0 ps  Iteration: 1  Instance: /tbench/u1_plasma/u1_cpu/u4_reg_bank/tri_port_mem
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
#    Time: 0 ps  Iteration: 1  Instance: /tbench/u1_plasma/opt_cache2/u_cache
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
#    Time: 0 ps  Iteration: 1  Instance: /tbench/u1_plasma/u1_cpu/u4_reg_bank
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
#    Time: 0 ps  Iteration: 1  Instance: /tbench/u1_plasma/u1_cpu/u4_reg_bank
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
#    Time: 0 ps  Iteration: 1  Instance: /tbench/u1_plasma/u1_cpu/u4_reg_bank
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
#    Time: 0 ps  Iteration: 1  Instance: /tbench/u1_plasma/u1_cpu/u4_reg_bank
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
#    Time: 0 ps  Iteration: 1  Instance: /tbench
# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0.
#    Time: 0 ps  Iteration: 1  Instance: /tbench
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
#    Time: 0 ps  Iteration: 2  Instance: /tbench/u1_plasma/u1_cpu/u4_reg_bank
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
#    Time: 0 ps  Iteration: 2  Instance: /tbench
# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0.
#    Time: 0 ps  Iteration: 2  Instance: /tbench
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
#    Time: 0 ps  Iteration: 2  Instance: /tbench/u1_plasma/opt_cache2/u_cache
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
#    Time: 0 ps  Iteration: 3  Instance: /tbench/u1_plasma/u1_cpu/u4_reg_bank/tri_port_mem
# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0.
#    Time: 0 ps  Iteration: 3  Instance: /tbench/u1_plasma/u1_cpu/u4_reg_bank/tri_port_mem
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
#    Time: 0 ps  Iteration: 3  Instance: /tbench/u1_plasma/u1_cpu/u4_reg_bank/tri_port_mem
# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0.
#    Time: 0 ps  Iteration: 3  Instance: /tbench/u1_plasma/u1_cpu/u4_reg_bank/tri_port_mem
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
#    Time: 0 ps  Iteration: 3  Instance: /tbench/u1_plasma/opt_cache2/u_cache
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
#    Time: 0 ps  Iteration: 4  Instance: /tbench/u1_plasma/u1_cpu/u4_reg_bank/tri_port_mem
# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0.
#    Time: 0 ps  Iteration: 4  Instance: /tbench/u1_plasma/u1_cpu/u4_reg_bank/tri_port_mem
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
#    Time: 0 ps  Iteration: 4  Instance: /tbench/u1_plasma/u1_cpu/u4_reg_bank/tri_port_mem
# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0.
#    Time: 0 ps  Iteration: 4  Instance: /tbench/u1_plasma/u1_cpu/u4_reg_bank/tri_port_mem
# Break key hit 
# Simulation stop requested.