EESchema Schematic File Version 2
LIBS:power,/home/cain/Embedded/ingenic/work/Qi/sakc/components/tlv1548,/home/cain/Embedded/ingenic/work/Qi/sakc/components/xc3sxxxe-tq144,../components/cy7c6801xa_128,device,conn,linear,regul,74xx,cmos4000,adc-dac,memory,xilinx,special,microcontrollers,dsp,microchip,analog_switches,motorola,texas,intel,audio,interface,digital-audio,philips,display,cypress,siliconi,contrib,valves,./SAKC.cache
EELAYER 24  0
EELAYER END
$Descr A4 11700 8267
Sheet 1 5
Title ""
Date "16 jan 2010"
Rev ""
Comp ""
Comment1 ""
Comment2 ""
Comment3 ""
Comment4 ""
$EndDescr
$Sheet
S 1450 3100 1350 500 
U 4B4D32EC
F0 "ANALOG_TO_DIGITAL" 60
F1 "ADC.sch" 60
$EndSheet
$Sheet
S 5800 3100 1350 500 
U 4B4D31AC
F0 "POWER_SUPPLY" 60
F1 "PWR_SUPPLY.sch" 60
$EndSheet
$Sheet
S 3700 2200 1900 2200
U 4B4D30DF
F0 "CPU" 60
F1 "CPU.sch" 60
F2 "D[0..7]" B L 3700 2550 60 
F3 "A[0..15]" B L 3700 2450 60 
F4 "CS" B L 3700 2650 60 
F5 "WR" B L 3700 2750 60 
F6 "RD" B L 3700 2850 60 
F7 "PSEN" B L 3700 3050 60 
F8 "OE" B L 3700 2950 60 
F9 "CFG_PROG" B L 3700 3300 60 
F10 "CFG_INIT" B L 3700 3200 60 
F11 "CFG_CCLK" B L 3700 3400 60 
F12 "CFG_RDWR" B L 3700 3500 60 
F13 "CFG_CS" B L 3700 3600 60 
F14 "CFG_BUSY" B L 3700 3700 60 
F15 "CFGD[0..7]" B L 3700 3800 60 
$EndSheet
$Sheet
S 3450 1050 1300 350 
U 4B4D2E7B
F0 "FPGA" 60
F1 "FPGA.sch" 60
$EndSheet
$EndSCHEMATC