`timescale 1ns / 1ps
module ADC(clk, sram_data, addr, nwe, ncs, noe, reset, led, ADC_EOC,
                ADC_SCLK, ADC_SDIN, ADC_SDOUT, ADC_CS, ADC_CSTART);
  
    parameter     B = (7);

    input       clk, addr, nwe, ncs, noe, reset, ADC_EOC;
    inout [B:0] sram_data;
    output      led, ADC_CS, ADC_CSTART, ADC_SCLK;
    inout 		ADC_SDIN, ADC_SDOUT;


    // Internal conection
    reg    led;

    // synchronize signals                               
    reg    		    sncs, snwe;
    reg     [10:0]  buffer_addr; 
    wire    [8:0]   addr2;
    reg     [B:0]	buffer_data;   

    // interfaz fpga signals    
    wire    [10:0]  addr;

    // bram interfaz signals
    reg    		    we;
    wire	    	we2;
    reg    		    w_st=0;
    reg     [B:0]   wrBus;
    wire    [B:0]   rdBus;
    wire    [B:0]   wrBus2;
    wire    [B:0]   rdBus2;

    reg     [25:0]  counter;
 
     // Test : LED blinking
    always @(posedge clk) begin
    if (reset)
      counter <= {25{1'b0}};
    else
      counter <= counter + 1;
	  led <=counter[25];
    end 
    
    // interefaz signals assignments
    wire   T = ~noe | ncs;
    assign sram_data = T?8'bZ:rdBus;

    // synchronize assignment
    always  @(negedge clk)
    begin
    sncs   <= ncs;
    snwe   <= nwe;
    buffer_data <= sram_data;
    buffer_addr <= addr;
    end

    // write access cpu to bram
    always @(posedge clk)
    if(reset) {w_st, we, wrBus} <= 0;
      else begin
        wrBus <= buffer_data;
        case (w_st)
          0: begin
              we <= 0;
              if(sncs | snwe) w_st <= 1;
          end
          1: begin
            if(~(sncs | snwe)) begin
              we    <= 1;
              w_st  <= 0;
            end	
            else we <= 0;
          end
        endcase
      end

    // Dual-port RAM instatiation
    RAMB16_S9_S9 ba0(
            .DOA(rdBus),                // Port A 8-bit Data Output
            .DOB(rdBus2),               // Port B 8-bit Data Output
            .DOPA(),                    // Port A 1-bit Parity Output
            .DOPB(),                    // Port B 1-bit Parity Output
            .ADDRA(buffer_addr[10:0]),  // Port A 11-bit Address Input
            .ADDRB(addr2[8:0]),         // Port B 11-bit Address Input
            .CLKA(~clk),                // Port A Clock
            .CLKB(~clk),                // Port B Clock
            .DIA(wrBus),                // Port A 8-bit Data Input
            .DIB(wrBus2),               // Port B 8-bit Data Input
            .DIPA(1'b0),                // Port A 1-bit parity Input
            .DIPB(1'b0),                // Port-B 1-bit parity Input
            .ENA(1'b1),                 // Port A RAM Enable Input
            .ENB(1'b1),                 // Port B RAM Enable Input
            .SSRA(1'b0),                // Port A Synchronous Set/Reset Input
            .SSRB(1'b0),                // Port B Synchronous Set/Reset Input
            .WEA(we),                   // Port A Write Enable Input
            .WEB(we2) );                // Port B Write Enable Input
					      
    // Peripheral instantiation
    ADC_peripheral  P1( clk, reset, ADC_EOC, ADC_CS, ADC_CSTART,
				        ADC_SCLK, ADC_SDIN, ADC_SDOUT, we2, 
				        rdBus2, wrBus2, addr2);
endmodule