---------------------------------------------------------------------
-- TITLE: Plasma (CPU core with memory)
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 6/4/02
-- FILENAME: plasma.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
--    Software 'as is' without warranty.  Author liable for nothing.
-- DESCRIPTION:
--    This entity combines the CPU core with memory and a UART.
--
-- Memory Map:
--   0x00000000 - 0x0000ffff   Internal RAM (8KB)
--   0x10000000 - 0x100fffff   External RAM (1MB)
--   Access all Misc registers with 32-bit accesses
--   0x20000000  Uart Write (will pause CPU if busy)
--   0x20000000  Uart Read
--   0x20000010  IRQ Mask
--   0x20000020  IRQ Status
--   0x20000030  GPIO0 Out Set bits
--   0x20000040  GPIO0 Out Clear bits
--   0x20000050  GPIOA In
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.mlite_pack.all;
library UNISIM;
use UNISIM.vcomponents.all;

entity plasma is
   generic(memory_type : string := "XILINX_16X");
   port(clk            : in std_logic;
        reset          : in std_logic;
        U_TxD          : out std_logic;
        U_RxD          : in std_logic;
        addr           : in std_logic_vector(12 downto 0);
        sram_data      : in std_logic_vector(7 downto 0);
        nwe            : in std_logic;
        noe            : in std_logic;
        ncs            : in std_logic;
        led            : out std_logic
   );
end; --entity plasma

architecture logic of plasma is
   signal address_next      : std_logic_vector(31 downto 0);
   signal byte_we_next      : std_logic_vector(3 downto 0);
   signal cpu_address       : std_logic_vector(31 downto 0);
   signal cpu_byte_we       : std_logic_vector(3 downto 0);
   signal cpu_data_w        : std_logic_vector(31 downto 0);
   signal cpu_data_r        : std_logic_vector(31 downto 0);
   signal cpu_pause         : std_logic;

   signal data_read_uart    : std_logic_vector(7 downto 0);

   signal cs_uart           : std_logic;
   signal uart_write_busy   : std_logic;
   signal uart_data_avail   : std_logic;
   signal irq_mask_reg      : std_logic_vector(7 downto 0);
   signal irq_status        : std_logic_vector(7 downto 0);
   signal irq               : std_logic;

   signal cs_ram            : std_logic;
   signal ram_address       : std_logic_vector(31 downto 2);
   signal ram_data_r        : std_logic_vector(31 downto 0);

   signal nreset            : std_logic;

begin  --architecture
--%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
--                     PROCESSOR
--%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
   u1_cpu: mlite_cpu 
      generic map (memory_type => memory_type)
      PORT MAP (
         clk          => clk,
         reset_in     => nreset,
         intr_in      => irq,
 
         address_next => address_next(31 downto 2),             --before rising_edge(clk)
         byte_we_next => byte_we_next,

         address      => cpu_address(31 downto 2), --after rising_edge(clk)
         byte_we      => cpu_byte_we,
         data_w       => cpu_data_w,
         data_r       => cpu_data_r,
         mem_pause    => cpu_pause);

   u2_ram: ram 
      port map (
         clk               => clk,
         enable            => cs_ram,
         write_byte_enable => byte_we_next,
         address           => ram_address(12 downto 2),
         data_write        => cpu_data_w,
         data_read         => ram_data_r);

   u3_uart: uart
      port map(
         clk          => clk,
         reset        => nreset,
         cs           => cs_uart,
         nRdWr        => cpu_byte_we(0),
         data_in      => cpu_data_w(7 downto 0),
         data_out     => data_read_uart,
         uart_read    => U_RxD,
         uart_write   => U_TxD,
         addr         => cpu_address(7 downto 4));

--%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
--                         ADDRESS DECODER
--%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
   cpu_pause                <= '0'; --(uart_write_busy and enable_uart and write_enable) or  --UART busy
   ram_address              <= ZERO(31 downto 13) & (address_next(12)) & address_next(11 downto 2);
   cpu_address(1 downto 0)  <= "00";
   address_next(1 downto 0) <= "00";

   nreset <= not(reset);


   led <= not(reset);

   addr_dec: process (cpu_address(30 downto 4))
   begin
     if (cpu_address(30 downto 28) = "000") then
       cs_ram     <= '1';
       cs_uart    <= '0';
     elsif  ( (cpu_address(30 downto 28) = "010") and ( (cpu_address(11 downto 8) = "0000") )) then
       cs_ram     <= '0';
       cs_uart    <= '1';
     else
       cs_ram     <= '0';
       cs_uart    <= '0';
     end if;
   end process;

   misc_proc: process(clk, nreset, cpu_address,
      ram_data_r, data_read_uart, cpu_pause,
      irq_mask_reg, irq_status, cpu_data_w)
   begin
      case cpu_address(30 downto 28) is
      when "000" =>         --internal RAM
         cpu_data_r <= ram_data_r;
      when "010" =>         --misc
         case cpu_address(6 downto 4) is
         when "000" =>      --uart
            cpu_data_r <= ZERO(31 downto 8) & data_read_uart;
         when "010" =>      --uart
            cpu_data_r <= ZERO(31 downto 8) & data_read_uart;
         when others =>
            cpu_data_r <= ZERO;
         end case;
      when others =>
         cpu_data_r <= ZERO;
      end case;
    end process;




end; --architecture logic