# //  ModelSim SE 6.0d Apr 25 2005 Linux 2.6.32-22-generic
# //
# //  Copyright Mentor Graphics Corporation 2005
# //              All Rights Reserved.
# //
# //  THIS WORK CONTAINS TRADE SECRET AND 
# //  PROPRIETARY INFORMATION WHICH IS THE PROPERTY
# //  OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS
# //  AND IS SUBJECT TO LICENSE TERMS.
# //
# do sram_bus_TIMING_TB.do 
# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim SE vlog 6.0d Compiler 2005.04 Apr 25 2005
# -- Compiling module sram_bus
# -- Compiling module glbl
# -- Compiling module sram_bus_TB
# ** Warning: glbl.v(5): 'glbl' already exists.
# -- Compiling module glbl
# 
# Top level modules:
# 	glbl
# 	sram_bus_TB
# vsim -L simprims_ver -L unisims_ver -L xilinxcorelib_ver -t 1ps sram_bus_TB glbl 
# Loading work.sram_bus_TB
# Loading work.sram_bus
# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_ONE
# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_ZERO
# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_FF
# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_SFF
# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_MUX2
# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_XOR2
# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_LUT2
# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_BUF
# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_LUT3
# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_INV
# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_RAMB16_S2
# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_BPAD
# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_IPAD
# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_OPAD
# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_CKBUF
# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_OBUFT
# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_OBUF
# Loading work.glbl
# ** Warning: (vsim-3017) ../sram_bus_TB.v(21): [TFMPC] - Too few port connections. Expected 8, found 7.
#         Region: /sram_bus_TB/uut
# ** Warning: (vsim-3015) ../sram_bus_TB.v(21): [PCDPC] - Port size (8 or 8) does not match connection size (1) for port 'sram_data'.
#         Region: /sram_bus_TB/uut
# ** Warning: (vsim-3722) ../sram_bus_TB.v(21): [TFMPC] - Missing connection for port 'led'.
# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.ffsrce
# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.sffsrce
# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.mux
# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.x_lut2_mux4
# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.x_lut3_mux4
# .main_pane.mdi.interior.cs.vm.paneset.cli_0.wf.clip.cs
# .main_pane.workspace
# .main_pane.signals.interior.cs
quit