image:     file format elf32-lm32

Sections:
Idx Name          Size      VMA       LMA       File off  Algn
  0 .text         00000270  00000000  00000000  00000054  2**2
                  CONTENTS, ALLOC, LOAD, CODE
  1 .rodata       0000001c  00000270  00000270  000002c4  2**2
                  CONTENTS, ALLOC, LOAD, READONLY, DATA
  2 .data         0000000c  0000028c  0000028c  000002e0  2**2
                  CONTENTS, ALLOC, LOAD, DATA
  3 .bss          00000004  00000298  00000298  000002ec  2**2
                  ALLOC
  4 .debug_abbrev 00000219  00000000  00000000  000002ec  2**0
                  CONTENTS, READONLY, DEBUGGING
  5 .debug_info   000003d0  00000000  00000000  00000505  2**0
                  CONTENTS, READONLY, DEBUGGING
  6 .debug_line   000002d8  00000000  00000000  000008d5  2**0
                  CONTENTS, READONLY, DEBUGGING
  7 .debug_frame  000000a0  00000000  00000000  00000bb0  2**2
                  CONTENTS, READONLY, DEBUGGING
  8 .debug_loc    000000fb  00000000  00000000  00000c50  2**0
                  CONTENTS, READONLY, DEBUGGING
  9 .debug_pubnames 000000bc  00000000  00000000  00000d4b  2**0
                  CONTENTS, READONLY, DEBUGGING
 10 .debug_aranges 00000040  00000000  00000000  00000e07  2**0
                  CONTENTS, READONLY, DEBUGGING
 11 .debug_ranges 00000018  00000000  00000000  00000e47  2**0
                  CONTENTS, READONLY, DEBUGGING
 12 .debug_str    0000017b  00000000  00000000  00000e5f  2**0
                  CONTENTS, READONLY, DEBUGGING
 13 .comment      00000011  00000000  00000000  00000fda  2**0
                  CONTENTS, READONLY

Disassembly of section .text:

00000000 <_ftext>:
   0:	98 00 00 00 	xor r0,r0,r0
   4:	d0 00 00 00 	wcsr IE,r0
   8:	78 01 00 00 	mvhi r1,0x0
   c:	38 21 00 00 	ori r1,r1,0x0
  10:	d0 e1 00 00 	wcsr EBA,r1
  14:	f8 00 00 03 	calli 20 <_crt0>
  18:	34 00 00 00 	nop
  1c:	34 00 00 00 	nop

00000020 <_crt0>:
  20:	78 1c 00 00 	mvhi sp,0x0
  24:	3b 9c 0f fc 	ori sp,sp,0xffc
  28:	78 1a 00 00 	mvhi gp,0x0
  2c:	3b 5a 02 a0 	ori gp,gp,0x2a0
  30:	78 01 00 00 	mvhi r1,0x0
  34:	38 21 02 98 	ori r1,r1,0x298
  38:	78 03 00 00 	mvhi r3,0x0
  3c:	38 63 02 9c 	ori r3,r3,0x29c

00000040 <.clearBSS>:
  40:	44 23 00 04 	be r1,r3,50 <.callMain>
  44:	58 20 00 00 	sw (r1+0),r0
  48:	34 21 00 04 	addi r1,r1,4
  4c:	e3 ff ff fd 	bi 40 <.clearBSS>

00000050 <.callMain>:
  50:	34 01 00 00 	mvi r1,0
  54:	34 02 00 00 	mvi r2,0
  58:	34 03 00 00 	mvi r3,0
  5c:	f8 00 00 1d 	calli d0 <main>

00000060 <irq_enable>:
  60:	34 01 00 01 	mvi r1,1
  64:	d0 01 00 00 	wcsr IE,r1
  68:	c3 a0 00 00 	ret

0000006c <irq_mask>:
  6c:	34 01 00 0f 	mvi r1,15
  70:	d0 21 00 00 	wcsr IM,r1
  74:	c3 a0 00 00 	ret

00000078 <irq_disable>:
  78:	34 01 00 00 	mvi r1,0
  7c:	d0 01 00 00 	wcsr IE,r1
  80:	c3 a0 00 00 	ret

00000084 <jump>:
  84:	c0 20 00 00 	b r1

00000088 <halt>:
  88:	e0 00 00 00 	bi 88 <halt>

0000008c <read_uint32>:
 */
#include "soc-hw.h"

/* prototypes */
uint32_t read_uint32()
{
  8c:	37 9c ff f8 	addi sp,sp,-8
  90:	5b 8b 00 08 	sw (sp+8),r11
  94:	5b 9d 00 04 	sw (sp+4),ra
	uint32_t val = 0, i;

    for (i = 0; i < 4; i++) {
        val <<= 8;
        val += (uint8_t)uart_getchar();
  98:	f8 00 00 57 	calli 1f4 <uart_getchar>
uint32_t read_uint32()
{
	uint32_t val = 0, i;

    for (i = 0; i < 4; i++) {
        val <<= 8;
  9c:	3c 2b 00 08 	sli r11,r1,8
        val += (uint8_t)uart_getchar();
  a0:	f8 00 00 55 	calli 1f4 <uart_getchar>
  a4:	b5 61 08 00 	add r1,r11,r1
uint32_t read_uint32()
{
	uint32_t val = 0, i;

    for (i = 0; i < 4; i++) {
        val <<= 8;
  a8:	3c 2b 00 08 	sli r11,r1,8
        val += (uint8_t)uart_getchar();
  ac:	f8 00 00 52 	calli 1f4 <uart_getchar>
  b0:	b5 61 08 00 	add r1,r11,r1
uint32_t read_uint32()
{
	uint32_t val = 0, i;

    for (i = 0; i < 4; i++) {
        val <<= 8;
  b4:	3c 2b 00 08 	sli r11,r1,8
        val += (uint8_t)uart_getchar();
  b8:	f8 00 00 4f 	calli 1f4 <uart_getchar>
    }

    return val;
}
  bc:	b5 61 08 00 	add r1,r11,r1
  c0:	2b 9d 00 04 	lw ra,(sp+4)
  c4:	2b 8b 00 08 	lw r11,(sp+8)
  c8:	37 9c 00 08 	addi sp,sp,8
  cc:	c3 a0 00 00 	ret

000000d0 <main>:

int main(int argc, char **argv)
{
  d0:	37 9c ff e4 	addi sp,sp,-28
  d4:	5b 8b 00 1c 	sw (sp+28),r11
  d8:	5b 8c 00 18 	sw (sp+24),r12
  dc:	5b 8d 00 14 	sw (sp+20),r13
  e0:	5b 8e 00 10 	sw (sp+16),r14
  e4:	5b 8f 00 0c 	sw (sp+12),r15
  e8:	5b 90 00 08 	sw (sp+8),r16
  ec:	5b 9d 00 04 	sw (sp+4),ra
	int8_t  *p;
	uint8_t  c;

	// Initialize UART
	uart_init();
  f0:	f8 00 00 40 	calli 1f0 <uart_init>

	c = '*'; // print msg on first iteration
	for(;;) {
		uint32_t start, size; 

		switch (c) {
  f4:	34 0d 00 67 	mvi r13,103
{
	int8_t  *p;
	uint8_t  c;

	// Initialize UART
	uart_init();
  f8:	34 01 00 2a 	mvi r1,42

	c = '*'; // print msg on first iteration
	for(;;) {
		uint32_t start, size; 

		switch (c) {
  fc:	34 0e 00 75 	mvi r14,117
 100:	34 0f 00 64 	mvi r15,100
    		case 'g': // goto
    			start = read_uint32();
    			jump(start);
    			break;   
		default:
			uart_putstr("**SAKC/bootloader** > \r\n");
 104:	78 10 00 00 	mvhi r16,0x0

	c = '*'; // print msg on first iteration
	for(;;) {
		uint32_t start, size; 

		switch (c) {
 108:	44 2d 00 08 	be r1,r13,128 <main+0x58>
 10c:	44 2e 00 16 	be r1,r14,164 <main+0x94>
 110:	44 2f 00 0a 	be r1,r15,138 <main+0x68>
    		case 'g': // goto
    			start = read_uint32();
    			jump(start);
    			break;   
		default:
			uart_putstr("**SAKC/bootloader** > \r\n");
 114:	ba 00 08 00 	mv r1,r16
 118:	38 21 02 70 	ori r1,r1,0x270
 11c:	f8 00 00 48 	calli 23c <uart_putstr>
			break;
		};
		c = uart_getchar();
 120:	f8 00 00 35 	calli 1f4 <uart_getchar>

	c = '*'; // print msg on first iteration
	for(;;) {
		uint32_t start, size; 

		switch (c) {
 124:	5c 2d ff fa 	bne r1,r13,10c <main+0x3c>
    			size  = read_uint32();
    			for (p = (int8_t *) start; p < (int8_t *) (start+size); p++)
				uart_putchar( *p );
    			break;
    		case 'g': // goto
    			start = read_uint32();
 128:	fb ff ff d9 	calli 8c <read_uint32>
    			jump(start);
 12c:	fb ff ff d6 	calli 84 <jump>
    			break;   
		default:
			uart_putstr("**SAKC/bootloader** > \r\n");
			break;
		};
		c = uart_getchar();
 130:	f8 00 00 31 	calli 1f4 <uart_getchar>
 134:	e3 ff ff fc 	bi 124 <main+0x54>
    			size  = read_uint32();
    			for (p = (int8_t *) start; p < (int8_t *) (start+size); p++)
    				*p = uart_getchar();
    			break;
		case 'd': // download
    			start = read_uint32();
 138:	fb ff ff d5 	calli 8c <read_uint32>
    			size  = read_uint32();
    			for (p = (int8_t *) start; p < (int8_t *) (start+size); p++)
 13c:	b8 20 58 00 	mv r11,r1
    			for (p = (int8_t *) start; p < (int8_t *) (start+size); p++)
    				*p = uart_getchar();
    			break;
		case 'd': // download
    			start = read_uint32();
    			size  = read_uint32();
 140:	fb ff ff d3 	calli 8c <read_uint32>
    			for (p = (int8_t *) start; p < (int8_t *) (start+size); p++)
 144:	b5 61 60 00 	add r12,r11,r1
 148:	51 6c ff f6 	bgeu r11,r12,120 <main+0x50>
				uart_putchar( *p );
 14c:	41 61 00 00 	lbu r1,(r11+0)
    				*p = uart_getchar();
    			break;
		case 'd': // download
    			start = read_uint32();
    			size  = read_uint32();
    			for (p = (int8_t *) start; p < (int8_t *) (start+size); p++)
 150:	35 6b 00 01 	addi r11,r11,1
				uart_putchar( *p );
 154:	f8 00 00 31 	calli 218 <uart_putchar>
    				*p = uart_getchar();
    			break;
		case 'd': // download
    			start = read_uint32();
    			size  = read_uint32();
    			for (p = (int8_t *) start; p < (int8_t *) (start+size); p++)
 158:	55 8b ff fd 	bgu r12,r11,14c <main+0x7c>
    			break;   
		default:
			uart_putstr("**SAKC/bootloader** > \r\n");
			break;
		};
		c = uart_getchar();
 15c:	f8 00 00 26 	calli 1f4 <uart_getchar>
 160:	e3 ff ff f1 	bi 124 <main+0x54>
	for(;;) {
		uint32_t start, size; 

		switch (c) {
    		case 'u': // upload 
    			start = read_uint32();
 164:	fb ff ff ca 	calli 8c <read_uint32>
    			size  = read_uint32();
    			for (p = (int8_t *) start; p < (int8_t *) (start+size); p++)
 168:	b8 20 58 00 	mv r11,r1
		uint32_t start, size; 

		switch (c) {
    		case 'u': // upload 
    			start = read_uint32();
    			size  = read_uint32();
 16c:	fb ff ff c8 	calli 8c <read_uint32>
    			for (p = (int8_t *) start; p < (int8_t *) (start+size); p++)
 170:	b5 61 60 00 	add r12,r11,r1
 174:	51 6c ff eb 	bgeu r11,r12,120 <main+0x50>
    				*p = uart_getchar();
 178:	f8 00 00 1f 	calli 1f4 <uart_getchar>
 17c:	31 61 00 00 	sb (r11+0),r1

		switch (c) {
    		case 'u': // upload 
    			start = read_uint32();
    			size  = read_uint32();
    			for (p = (int8_t *) start; p < (int8_t *) (start+size); p++)
 180:	35 6b 00 01 	addi r11,r11,1
 184:	55 8b ff fd 	bgu r12,r11,178 <main+0xa8>
    			break;   
		default:
			uart_putstr("**SAKC/bootloader** > \r\n");
			break;
		};
		c = uart_getchar();
 188:	f8 00 00 1b 	calli 1f4 <uart_getchar>
 18c:	e3 ff ff e6 	bi 124 <main+0x54>

00000190 <sleep>:
void sleep(int msec)
{
	uint32_t tcr;

	// Use timer0.1
	timer0->compare1 = (FCPU/1000)*msec;
 190:	78 02 00 00 	mvhi r2,0x0
 194:	38 42 02 90 	ori r2,r2,0x290
 198:	38 03 c3 50 	mvu r3,0xc350
 19c:	28 42 00 00 	lw r2,(r2+0)
 1a0:	88 23 08 00 	mul r1,r1,r3
 1a4:	58 41 00 10 	sw (r2+16),r1
	timer0->counter1 = 0;
 1a8:	34 01 00 00 	mvi r1,0
 1ac:	58 41 00 14 	sw (r2+20),r1
	timer0->tcr1 = TIMER_EN | TIMER_IRQEN;
 1b0:	34 01 00 0a 	mvi r1,10
 1b4:	58 41 00 0c 	sw (r2+12),r1

	do {
		//halt();
 		tcr = timer0->tcr1;
 1b8:	28 41 00 0c 	lw r1,(r2+12)
 	} while ( ! (tcr & TIMER_TRIG) );
 1bc:	20 21 00 01 	andi r1,r1,0x1
 1c0:	44 20 ff fe 	be r1,r0,1b8 <sleep+0x28>
}
 1c4:	c3 a0 00 00 	ret

000001c8 <tic_init>:

void tic_init()
{
	// Setup timer0.0
	timer0->compare0 = (FCPU/1000);
 1c8:	78 01 00 00 	mvhi r1,0x0
 1cc:	38 21 02 90 	ori r1,r1,0x290
 1d0:	28 21 00 00 	lw r1,(r1+0)
 1d4:	38 02 c3 50 	mvu r2,0xc350
 1d8:	58 22 00 04 	sw (r1+4),r2
	timer0->counter0 = 0;
 1dc:	34 02 00 00 	mvi r2,0
 1e0:	58 22 00 08 	sw (r1+8),r2
	timer0->tcr0     = TIMER_EN | TIMER_AR | TIMER_IRQEN;
 1e4:	34 02 00 0e 	mvi r2,14
 1e8:	58 22 00 00 	sw (r1+0),r2
}
 1ec:	c3 a0 00 00 	ret

000001f0 <uart_init>:
	//uart0->lcr = 0x03;  // Line Control Register:    8N1
	//uart0->mcr = 0x00;  // Modem Control Register

	// Setup Divisor register (Fclk / Baud)
	//uart0->div = (FCPU/(57600*16));
}
 1f0:	c3 a0 00 00 	ret

000001f4 <uart_getchar>:

char uart_getchar()
{   
 1f4:	78 01 00 00 	mvhi r1,0x0
 1f8:	38 21 02 8c 	ori r1,r1,0x28c
 1fc:	28 22 00 00 	lw r2,(r1+0)
	while (! (uart0->ucr & UART_DR)) ;
 200:	28 41 00 00 	lw r1,(r2+0)
 204:	20 21 00 01 	andi r1,r1,0x1
 208:	44 20 ff fe 	be r1,r0,200 <uart_getchar+0xc>
	return uart0->rxtx;
 20c:	28 41 00 04 	lw r1,(r2+4)
}
 210:	20 21 00 ff 	andi r1,r1,0xff
 214:	c3 a0 00 00 	ret

00000218 <uart_putchar>:

void uart_putchar(char c)
{
 218:	78 02 00 00 	mvhi r2,0x0
 21c:	38 42 02 8c 	ori r2,r2,0x28c
 220:	28 43 00 00 	lw r3,(r2+0)
 224:	20 21 00 ff 	andi r1,r1,0xff
	while (uart0->ucr & UART_BUSY) ;
 228:	28 62 00 00 	lw r2,(r3+0)
 22c:	20 42 00 10 	andi r2,r2,0x10
 230:	5c 40 ff fe 	bne r2,r0,228 <uart_putchar+0x10>
	uart0->rxtx = c;
 234:	58 61 00 04 	sw (r3+4),r1
}
 238:	c3 a0 00 00 	ret

0000023c <uart_putstr>:

void uart_putstr(char *str)
{
	char *c = str;
	while(*c) {
 23c:	40 24 00 00 	lbu r4,(r1+0)
 240:	44 80 00 0b 	be r4,r0,26c <uart_putstr+0x30>
 244:	78 02 00 00 	mvhi r2,0x0
 248:	38 42 02 8c 	ori r2,r2,0x28c
 24c:	28 43 00 00 	lw r3,(r2+0)
	return uart0->rxtx;
}

void uart_putchar(char c)
{
	while (uart0->ucr & UART_BUSY) ;
 250:	28 62 00 00 	lw r2,(r3+0)
 254:	20 42 00 10 	andi r2,r2,0x10
 258:	5c 40 ff fe 	bne r2,r0,250 <uart_putstr+0x14>
	uart0->rxtx = c;
 25c:	58 64 00 04 	sw (r3+4),r4
void uart_putstr(char *str)
{
	char *c = str;
	while(*c) {
		uart_putchar(*c);
		c++;
 260:	34 21 00 01 	addi r1,r1,1
}

void uart_putstr(char *str)
{
	char *c = str;
	while(*c) {
 264:	40 24 00 00 	lbu r4,(r1+0)
 268:	5c 82 ff fa 	bne r4,r2,250 <uart_putstr+0x14>
 26c:	c3 a0 00 00 	ret