/* ADC Peripheral.h

Copyright (C) 2010             Carlos Camargo  cicamargoba@unal.edu.co
							   Andres Calderon andres.calderon@emqbit.com

This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.

This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
GNU General Public License for more details.

You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA */

#ifndef __adc_peripheral_h__
#define __adc_peripheral_h__

#include "jz47xx_mmap.h"
#include "jz47xx_gpio.h"

#define ADC_CMD_NONE             0x00 /* Nothing to do                        */
#define ADC_CMD_SET_SPI_CLKDIV   0x90 /* Set clock divider for ADC sclk       */

#define ADC_CMD_SET_CHANNEL0     0x50 /* Set channel 0                        */
#define ADC_CMD_READ_CHANNEL0    0x60 /* Read channel 0                       */

#define ADC_CMD_SET_CHANNEL1     0x51 /* Set channel 1                        */
#define ADC_CMD_READ_CHANNEL1    0x61 /* Read channel 1                       */

#define ADC_CMD_SET_CHANNEL2     0x52 /* Set channel 2                        */
#define ADC_CMD_READ_CHANNEL2    0x62 /* Read channel 2                       */

#define ADC_CMD_SET_CHANNEL3     0x53 /* Set channel 3                        */
#define ADC_CMD_READ_CHANNEL3    0x63 /* Read channel 3                       */

#define ADC_CMD_SET_CHANNEL4     0x54 /* Set channel 4                        */
#define ADC_CMD_READ_CHANNEL4    0x64 /* Read channel 4                       */

#define ADC_CMD_SET_CHANNEL5     0x55 /* Set channel 5                        */
#define ADC_CMD_READ_CHANNEL5    0x65 /* Read channel 5                       */

#define ADC_CMD_SET_CHANNEL6     0x56 /* Set channel 6                        */
#define ADC_CMD_READ_CHANNEL6    0x66 /* Read channel 6                       */

#define ADC_CMD_SET_CHANNEL7     0x57 /* Set channel 7                        */
#define ADC_CMD_READ_CHANNEL7    0x67 /* Read channel 8                       */

#define ADC_CMD_SET_POWER_DOWN   0X58 /* Set ADC power down mode  (1uA)       */

#define ADC_CMD_SET_FAST_CONV    0X59 /* Initialize ADC Fast Convertion(<10us)*/

#define ADC_CMD_SET_LOW_CONV     0X5A /* Initialize ADC Fast Convertion(<40us)*/

#define ADC_CMD_SET_AUTOSELFT_1  0x5B /* Set Autoselft ADC {(Vref+)-(Vref-)}/2*/
#define ADC_CMD_READ_AUTOSELFT_1 0x6B /* Read Autoselft ADC 1 (0x0200)        */

#define ADC_CMD_SET_AUTOSELFT_2  0x5C /* Set Autoselft ADC (Vref-)            */
#define ADC_CMD_READ_AUTOSELFT_2 0x6C /* Read Autoselft ADC 2 (0x0000)        */

#define ADC_CMD_SET_AUTOSELFT_3  0x5D /* Set Autoselft ADC (Vref+)            */
#define ADC_CMD_READ_AUTOSELFT_3 0x6D /* Read Autoselft ADC 3 (0x03FF)        */

#define ADC_SPI_CLKDIV_MIN       0x14 /* 50/(2*20) -> 1.25MHz (MAX=2.8MHz)    */
#define ADC_SPI_CLKDIV_MAX       0xFF /* 50/(2*255) -> 98.04KHz               */

#define ADC_MAX_BUFFER           0x3FE/* 1022 reads/commands                  */

#define CS2_PORT				 JZ_GPIO_PORT_B
#define CS2_PIN					 26

typedef unsigned char uchar;

JZ_REG *jz_adc_init();

void jz_adc_config(JZ_REG * addr, int BUFFER, uchar CLK_DIV, uchar CMD);

int jz_adc_check_buffer(JZ_REG * addr);

#endif