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nn-usb-fpga/UART/logic/build/project.mrp
carlos 62d0edf217 Adding PS2, capacitive keyboard examples
2010-11-30 19:26:56 -05:00

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Release 10.1.03 Map K.39 (lin)
Xilinx Mapping Report File for Design 'uart_peripheral'
Design Information
------------------
Command Line : map -pr b -p xc3s500e-VQ100-4 project.ngd
Target Device : xc3s500e
Target Package : vq100
Target Speed : -4
Mapper Version : spartan3e -- $Revision: 1.46.12.2 $
Mapped Date : Thu Nov 11 14:37:58 2010
Design Summary
--------------
Number of errors: 0
Number of warnings: 2
Logic Utilization:
Number of Slice Flip Flops: 157 out of 9,312 1%
Number of 4 input LUTs: 141 out of 9,312 1%
Logic Distribution:
Number of occupied Slices: 138 out of 4,656 2%
Number of Slices containing only related logic: 138 out of 138 100%
Number of Slices containing unrelated logic: 0 out of 138 0%
*See NOTES below for an explanation of the effects of unrelated logic.
Total Number of 4 input LUTs: 181 out of 9,312 1%
Number used as logic: 141
Number used as a route-thru: 40
Number of bonded IOBs: 20 out of 66 30%
IOB Flip Flops: 16
Number of BUFGMUXs: 1 out of 24 4%
Peak Memory Usage: 152 MB
Total REAL time to MAP completion: 10 secs
Total CPU time to MAP completion: 8 secs
NOTES:
Related logic is defined as being logic that shares connectivity - e.g. two
LUTs are "related" if they share common inputs. When assembling slices,
Map gives priority to combine logic that is related. Doing so results in
the best timing performance.
Unrelated logic shares no connectivity. Map will only begin packing
unrelated logic into a slice once 99% of the slices are occupied through
related logic packing.
Note that once logic distribution reaches the 99% level through related
logic packing, this does not mean the device is completely utilized.
Unrelated logic packing will then begin, continuing until all usable LUTs
and FFs are occupied. Depending on your timing budget, increased levels of
unrelated logic packing may adversely affect the overall timing performance
of your design.
Table of Contents
-----------------
Section 1 - Errors
Section 2 - Warnings
Section 3 - Informational
Section 4 - Removed Logic Summary
Section 5 - Removed Logic
Section 6 - IOB Properties
Section 7 - RPMs
Section 8 - Guide Report
Section 9 - Area Group and Partition Summary
Section 10 - Modular Design Summary
Section 11 - Timing Report
Section 12 - Configuration String Information
Section 13 - Control Set Information
Section 14 - Utilization by Hierarchy
Section 1 - Errors
------------------
Section 2 - Warnings
--------------------
WARNING:LIT:243 - Logical network RxD2 has no load.
WARNING:LIT:395 - The above warning message base_net_load_rule is repeated 1
more times for the following (max. 5 shown):
TxD2
To see the details of these warning messages, please use the -detail switch.
Section 3 - Informational
-------------------------
INFO:MapLib:564 - The following environment variables are currently set:
INFO:MapLib:591 - XIL_MAP_LOCWARN Value: 1
INFO:LIT:244 - All of the single ended outputs in this design are using slew
rate limited output drivers. The delay on speed critical single ended outputs
can be dramatically reduced by designating them as fast outputs.
Section 4 - Removed Logic Summary
---------------------------------
2 block(s) optimized away
Section 5 - Removed Logic
-------------------------
Optimized Block(s):
TYPE BLOCK
GND XST_GND
VCC XST_VCC
To enable printing of redundant blocks removed and signals merged, set the
detailed map report option and rerun map.
Section 6 - IOB Properties
--------------------------
+-------------------------------------------------------------------------------------------------------------------------------------------------+
| IOB Name | Type | Direction | IO Standard | Drive | Slew | Reg (s) | Resistor | IOB |
| | | | | Strength | Rate | | | Delay |
+-------------------------------------------------------------------------------------------------------------------------------------------------+
| RxD | IBUF | INPUT | LVCMOS25 | | | IFF1 | | 0 / 3 |
| TxD | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | OFF1 | | 0 / 0 |
| addr<0> | IBUF | INPUT | LVCMOS25 | | | IFF1 | | 0 / 3 |
| addr<1> | IBUF | INPUT | LVCMOS25 | | | IFF1 | | 0 / 3 |
| addr<2> | IBUF | INPUT | LVCMOS25 | | | IFF1 | | 0 / 3 |
| clk | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 |
| irq_pin | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 |
| led | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | OFF1 | | 0 / 0 |
| ncs | IBUF | INPUT | LVCMOS25 | | | IFF1 | | 0 / 3 |
| noe | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 |
| nwe | IBUF | INPUT | LVCMOS25 | | | IFF1 | | 0 / 3 |
| reset | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 |
| sram_data<0> | IOB | BIDIR | LVCMOS25 | 12 | SLOW | IFF1 | | 0 / 3 |
| sram_data<1> | IOB | BIDIR | LVCMOS25 | 12 | SLOW | IFF1 | | 0 / 3 |
| sram_data<2> | IOB | BIDIR | LVCMOS25 | 12 | SLOW | IFF1 | | 0 / 3 |
| sram_data<3> | IOB | BIDIR | LVCMOS25 | 12 | SLOW | IFF1 | | 0 / 3 |
| sram_data<4> | IOB | BIDIR | LVCMOS25 | 12 | SLOW | IFF1 | | 0 / 3 |
| sram_data<5> | IOB | BIDIR | LVCMOS25 | 12 | SLOW | IFF1 | | 0 / 3 |
| sram_data<6> | IOB | BIDIR | LVCMOS25 | 12 | SLOW | IFF1 | | 0 / 3 |
| sram_data<7> | IOB | BIDIR | LVCMOS25 | 12 | SLOW | IFF1 | | 0 / 3 |
+-------------------------------------------------------------------------------------------------------------------------------------------------+
Section 7 - RPMs
----------------
Section 8 - Guide Report
------------------------
Guide not run on this design.
Section 9 - Area Group and Partition Summary
--------------------------------------------
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
Area Group Information
----------------------
No area groups were found in this design.
----------------------
Section 10 - Modular Design Summary
-----------------------------------
Modular Design not used for this design.
Section 11 - Timing Report
--------------------------
This design was not run using timing mode.
Section 12 - Configuration String Details
-----------------------------------------
Use the "-detail" map option to print out Configuration Strings
Section 13 - Control Set Information
------------------------------------
No control set information for this architecture.
Section 14 - Utilization by Hierarchy
-------------------------------------
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
| Module | Partition | Slices | Slice Reg | LUTs | LUTRAM | BRAM | MULT18X18 | BUFG | DCM | Full Hierarchical Name |
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
| uart_peripheral/ | | 35/165 | 34/157 | 47/181 | 0/0 | 0/0 | 0/0 | 1/1 | 0/0 | uart_peripheral |
| +UART | | 0/130 | 0/123 | 0/134 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | uart_peripheral/UART |
| ++buffrx1 | | 14/14 | 20/20 | 5/5 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | uart_peripheral/UART/buffrx1 |
| ++bufftx1 | | 12/12 | 17/17 | 14/14 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | uart_peripheral/UART/bufftx1 |
| ++ctrl_rx1 | | 3/3 | 5/5 | 6/6 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | uart_peripheral/UART/ctrl_rx1 |
| ++ctrl_tx1 | | 6/6 | 6/6 | 10/10 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | uart_peripheral/UART/ctrl_tx1 |
| ++dato_rdy1 | | 3/3 | 2/2 | 2/2 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | uart_peripheral/UART/dato_rdy1 |
| ++div161 | | 3/3 | 4/4 | 4/4 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | uart_peripheral/UART/div161 |
| ++div27 | | 5/5 | 6/6 | 9/9 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | uart_peripheral/UART/div27 |
| ++div_ms1 | | 31/31 | 33/33 | 27/27 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | uart_peripheral/UART/div_ms1 |
| ++ier1 | | 3/3 | 3/3 | 2/2 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | uart_peripheral/UART/ier1 |
| ++if_arm1 | | 18/18 | 0/0 | 30/30 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | uart_peripheral/UART/if_arm1 |
| ++ifrxd1 | | 1/1 | 2/2 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | uart_peripheral/UART/ifrxd1 |
| ++isr1 | | 14/14 | 8/8 | 13/13 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | uart_peripheral/UART/isr1 |
| ++lcr1 | | 4/4 | 8/8 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | uart_peripheral/UART/lcr1 |
| ++muestreo1 | | 7/7 | 6/6 | 8/8 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | uart_peripheral/UART/muestreo1 |
| ++pulso1 | | 2/2 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | uart_peripheral/UART/pulso1 |
| ++pulso2 | | 2/2 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | uart_peripheral/UART/pulso2 |
| ++pulso3 | | 2/2 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | uart_peripheral/UART/pulso3 |
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
* Slices can be packed with basic elements from multiple hierarchies.
Therefore, a slice will be counted in every hierarchical module
that each of its packed basic elements belong to.
** For each column, there are two numbers reported <A>/<B>.
<A> is the number of elements that belong to that specific hierarchical module.
<B> is the total number of elements from that hierarchical module and any lower level
hierarchical modules below.
*** The LUTRAM column counts all LUTs used as memory including RAM, ROM, and shift registers.
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