132 lines
3.9 KiB
Makefile
132 lines
3.9 KiB
Makefile
VINCDIR= \
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-I../rtl/wb_conbus \
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-I../rtl/lm32 \
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-I../rtl/wb_ddr
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SYN_SRC=
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SIM_SRC= \
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system_tb.v \
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../sim/sram/sram16.v \
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../sim/unisims/BUFG.v \
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../sim/unisims/DCM.v
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SRC= \
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../system.v \
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../rtl/lac/lac.v \
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../rtl/lac/uart.v \
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../rtl/lac/dp_ram.v \
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../rtl/lm32/lm32_cpu.v \
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../rtl/lm32/lm32_instruction_unit.v \
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../rtl/lm32/lm32_decoder.v \
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../rtl/lm32/lm32_simtrace.v \
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../rtl/lm32/lm32_load_store_unit.v \
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../rtl/lm32/lm32_adder.v \
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../rtl/lm32/lm32_addsub.v \
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../rtl/lm32/lm32_logic_op.v \
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../rtl/lm32/lm32_shifter.v \
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../rtl/lm32/lm32_multiplier.v \
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../rtl/lm32/lm32_mc_arithmetic.v \
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../rtl/lm32/lm32_interrupt.v \
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../rtl/lm32/lm32_icache.v \
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../rtl/lm32/lm32_dcache.v \
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../rtl/lm32/lm32_ram.v \
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../rtl/wb_bram/wb_bram.v \
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../rtl/wb_uart/wb_uart.v \
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../rtl/wb_timer/wb_timer.v \
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../rtl/wb_gpio/wb_gpio.v \
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../rtl/wb_conbus/wb_conbus_top.v \
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../rtl/wb_conbus/wb_conbus_arb.v \
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../rtl/wb_sram/wb_sram32.v
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#############################################################################
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# Synthesis constants
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SYNCLEAN=system.bgn system.drc system.mrp system.ngd system.pcf
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SYNCLEAN+=system.bld system.lso system.ncd system.ngm system.srp
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SYNCLEAN+=system.bit system_signalbrowser.* system-routed_pad.tx
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SYNCLEAN+=system.map system_summary.xml timing.twr
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SYNCLEAN+=system-routed* system_usage* system.ngc param.opt netlist.lst
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SYNCLEAN+=xst system.prj *ngr *xrpt _xmsgs xlnx_auto_0_xdb *html *log *xwbt
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USAGE_DEPTH=0
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SMARTGUIDE=
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#############################################################################
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# Simulation constants
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SIMCLEAN=system_tb.vvp system_tb.vcd verilog.log system_tb.vvp.list simulation
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CVER=cver
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GTKWAVE=gtkwave
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IVERILOG=iverilog
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VVP=vvp
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#############################################################################
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#
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sim: system_tb.vcd
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syn: system.bit
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view: system_tb.view
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#############################################################################
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# Ikarus verilog simulation
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system_tb.vvp:
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rm -rf simulation && mkdir simulation
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cp system_tb.v system_conf.v simulation && cd simulation && rm -f $@.list
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for i in $(SRC); do echo $$i >> simulation/$@.list; done
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for i in $(SIM_SRC); do echo $$i >> simulation/$@.list; done
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cd simulation && $(IVERILOG) -o $@ $(VINCDIR) -c $@.list -s $(@:.vvp=)
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%.vcd: %.vvp
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cd simulation && $(VVP) $<
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#############################################################################
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# ISE Synthesis
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system.prj:
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rm -rf build && mkdir build
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@rm -f $@
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for i in $(SRC); do echo verilog work $$i >> build/$@; done
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for i in $(SRC_HDL); do echo VHDL work $$i >> build/$@; done
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system.ngc: system.prj
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cd build && xst -ifn ../system.xst
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system.ngd: system.ngc system.ucf
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cd build && ngdbuild -uc ../system.ucf system.ngc
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system.ncd: system.ngd
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cd build && map $(SMARTGUIDE) system.ngd
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system-routed.ncd: system.ncd
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cd build && par $(SMARTGUIDE) -ol high -w system.ncd system-routed.ncd
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system.bit: system-routed.ncd
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cd build && bitgen -w system-routed.ncd system.bit
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@mv -f build/system.bit $@
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system.mcs: system.bit
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cd build && promgen -u 0 system
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system-routed.xdl: system-routed.ncd
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cd build && xdl -ncd2xdl system-routed.ncd system-routed.xdl
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system-routed.twr: system-routed.ncd
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cd build && trce -v 10 system-routed.ncd system.pcf
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timing: system-routed.twr
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usage: system-routed.xdl
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xdlanalyze.pl system-routed.xdl $(USAGE_DEPTH)
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####################################################################
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# final targets
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%.view: %.vcd
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cd simulation && $(GTKWAVE) $< $<.save
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clean:
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rm -Rf build $(SYNCLEAN) $(SIMCLEAN)
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.PHONY: clean view
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