mirror of
git://projects.qi-hardware.com/nn-usb-fpga.git
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43 lines
2.6 KiB
Verilog
43 lines
2.6 KiB
Verilog
/////////////////////////////////////////////////////////////////////
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//// ////
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//// WISHBONE Connection ShareBus Definitions ////
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//// ////
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//// ////
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//// Author: Johny Chi ////
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//// chisuhua@yahoo.com.cn ////
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//// ////
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//// ////
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//// Downloaded from: http://www.opencores.org/cores/wb_conmax/ ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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/// ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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`timescale 1ns / 10ps
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