46 lines
1.3 KiB
Verilog
46 lines
1.3 KiB
Verilog
//---------------------------------------------------------------------------
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//
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// This file is used by ../rtl/lm32/* to configure CPU parameter
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//
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//---------------------------------------------------------------------------
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`ifndef SYSTEM_CONF
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`define SYSTEM_CONF
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`define INCLUDE_LM32
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//`timescale 1ns / 100 ps
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`define CFG_EBA_RESET 32'h0
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`define CFG_DEBA_RESET 32'h0
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`define CFG_PL_MULTIPLY_ENABLED
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`define CFG_PL_BARREL_SHIFT_ENABLED
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`define CFG_SIGN_EXTEND_ENABLED
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`define CFG_MC_DIVIDE_ENABLED
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// Instruction Cache
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// [0x00000000,0x80000000) cachable
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// [0x80000000,0xffffffff] non-cachabel
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`define CFG_ICACHE_ENABLED
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`define CFG_ICACHE_ASSOCIATIVITY 1
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`define CFG_ICACHE_SETS 512
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`define CFG_ICACHE_BYTES_PER_LINE 16
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`define CFG_ICACHE_BASE_ADDRESS 32'h0
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`define CFG_ICACHE_LIMIT 32'h7fffffff
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// Data Cache
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// [0x00000000,0x80000000) cachable
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// [0x80000000,0xffffffff] non-cachabel
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// `define CFG_DCACHE_ENABLED
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`define CFG_DCACHE_ASSOCIATIVITY 1
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`define CFG_DCACHE_SETS 512
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`define CFG_DCACHE_BYTES_PER_LINE 16
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`define CFG_DCACHE_BASE_ADDRESS 32'h0
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`define CFG_DCACHE_LIMIT 32'h7fffffff
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// `define CFG_DEBUG_ENABLED
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// `define CFG_ROM_DEBUG_ENABLED
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// `define CFG_BREAKPOINTS 32'h1
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// `define CFG_WATCHPOINTS 32'h1
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`endif // SYSTEM_CONF
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