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324 lines
14 KiB
VHDL
324 lines
14 KiB
VHDL
---------------------------------------------------------------------
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-- TITLE: Register Bank
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-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
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-- DATE CREATED: 2/2/01
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-- FILENAME: reg_bank.vhd
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-- PROJECT: Plasma CPU core
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-- COPYRIGHT: Software placed into the public domain by the author.
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-- Software 'as is' without warranty. Author liable for nothing.
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-- DESCRIPTION:
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-- Implements a register bank with 32 registers that are 32-bits wide.
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-- There are two read-ports and one write port.
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---------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use work.mlite_pack.all;
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--library UNISIM; --May need to uncomment for ModelSim
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--use UNISIM.vcomponents.all; --May need to uncomment for ModelSim
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entity reg_bank is
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generic(memory_type : string := "XILINX_16X");
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port(clk : in std_logic;
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reset_in : in std_logic;
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pause : in std_logic;
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rs_index : in std_logic_vector(5 downto 0);
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rt_index : in std_logic_vector(5 downto 0);
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rd_index : in std_logic_vector(5 downto 0);
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reg_source_out : out std_logic_vector(31 downto 0);
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reg_target_out : out std_logic_vector(31 downto 0);
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reg_dest_new : in std_logic_vector(31 downto 0);
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intr_enable : out std_logic);
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end; --entity reg_bank
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--------------------------------------------------------------------
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-- The ram_block architecture attempts to use TWO dual-port memories.
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-- Different FPGAs and ASICs need different implementations.
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-- Choose one of the RAM implementations below.
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-- I need feedback on this section!
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--------------------------------------------------------------------
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architecture ram_block of reg_bank is
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signal intr_enable_reg : std_logic;
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type ram_type is array(31 downto 0) of std_logic_vector(31 downto 0);
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--controls access to dual-port memories
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signal addr_read1, addr_read2 : std_logic_vector(4 downto 0);
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signal addr_write : std_logic_vector(4 downto 0);
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signal data_out1, data_out2 : std_logic_vector(31 downto 0);
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signal write_enable : std_logic;
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begin
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reg_proc: process(clk, rs_index, rt_index, rd_index, reg_dest_new,
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intr_enable_reg, data_out1, data_out2, reset_in, pause)
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begin
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--setup for first dual-port memory
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if rs_index = "101110" then --reg_epc CP0 14
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addr_read1 <= "00000";
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else
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addr_read1 <= rs_index(4 downto 0);
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end if;
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case rs_index is
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when "000000" => reg_source_out <= ZERO;
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when "101100" => reg_source_out <= ZERO(31 downto 1) & intr_enable_reg;
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--interrupt vector address = 0x3c
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when "111111" => reg_source_out <= ZERO(31 downto 8) & "00111100";
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when others => reg_source_out <= data_out1;
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end case;
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--setup for second dual-port memory
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addr_read2 <= rt_index(4 downto 0);
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case rt_index is
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when "000000" => reg_target_out <= ZERO;
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when others => reg_target_out <= data_out2;
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end case;
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--setup write port for both dual-port memories
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if rd_index /= "000000" and rd_index /= "101100" and pause = '0' then
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write_enable <= '1';
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else
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write_enable <= '0';
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end if;
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if rd_index = "101110" then --reg_epc CP0 14
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addr_write <= "00000";
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else
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addr_write <= rd_index(4 downto 0);
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end if;
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if reset_in = '1' then
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intr_enable_reg <= '0';
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elsif rising_edge(clk) then
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if rd_index = "101110" then --reg_epc CP0 14
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intr_enable_reg <= '0'; --disable interrupts
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elsif rd_index = "101100" then
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intr_enable_reg <= reg_dest_new(0);
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end if;
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end if;
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intr_enable <= intr_enable_reg;
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end process;
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--------------------------------------------------------------
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---- Pick only ONE of the dual-port RAM implementations below!
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--------------------------------------------------------------
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-- Option #1
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-- One tri-port RAM, two read-ports, one write-port
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-- 32 registers 32-bits wide
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tri_port_mem:
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if memory_type = "TRI_PORT_X" generate
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ram_proc: process(clk, addr_read1, addr_read2,
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addr_write, reg_dest_new, write_enable)
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variable tri_port_ram : ram_type := (others => ZERO);
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begin
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data_out1 <= tri_port_ram(conv_integer(addr_read1));
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data_out2 <= tri_port_ram(conv_integer(addr_read2));
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if rising_edge(clk) then
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if write_enable = '1' then
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tri_port_ram(conv_integer(addr_write)) := reg_dest_new;
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end if;
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end if;
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end process;
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end generate; --tri_port_mem
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-- Option #2
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-- Two dual-port RAMs, each with one read-port and one write-port
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dual_port_mem:
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if memory_type = "DUAL_PORT_" generate
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ram_proc2: process(clk, addr_read1, addr_read2,
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addr_write, reg_dest_new, write_enable)
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variable dual_port_ram1 : ram_type := (others => ZERO);
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variable dual_port_ram2 : ram_type := (others => ZERO);
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begin
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data_out1 <= dual_port_ram1(conv_integer(addr_read1));
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data_out2 <= dual_port_ram2(conv_integer(addr_read2));
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if rising_edge(clk) then
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if write_enable = '1' then
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dual_port_ram1(conv_integer(addr_write)) := reg_dest_new;
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dual_port_ram2(conv_integer(addr_write)) := reg_dest_new;
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end if;
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end if;
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end process;
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end generate; --dual_port_mem
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-- Option #3
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-- RAM16X1D: 16 x 1 positive edge write, asynchronous read dual-port
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-- distributed RAM for all Xilinx FPGAs
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-- From library UNISIM; use UNISIM.vcomponents.all;
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xilinx_16x1d:
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if memory_type = "XILINX_16X" generate
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signal data_out1A, data_out1B : std_logic_vector(31 downto 0);
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signal data_out2A, data_out2B : std_logic_vector(31 downto 0);
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signal weA, weB : std_logic;
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signal no_connect : std_logic_vector(127 downto 0);
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begin
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weA <= write_enable and not addr_write(4); --lower 16 registers
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weB <= write_enable and addr_write(4); --upper 16 registers
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reg_loop: for i in 0 to 31 generate
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begin
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--Read port 1 lower 16 registers
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reg_bit1a : RAM16X1D
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port map (
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WCLK => clk, -- Port A write clock input
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WE => weA, -- Port A write enable input
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A0 => addr_write(0), -- Port A address[0] input bit
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A1 => addr_write(1), -- Port A address[1] input bit
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A2 => addr_write(2), -- Port A address[2] input bit
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A3 => addr_write(3), -- Port A address[3] input bit
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D => reg_dest_new(i), -- Port A 1-bit data input
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DPRA0 => addr_read1(0), -- Port B address[0] input bit
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DPRA1 => addr_read1(1), -- Port B address[1] input bit
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DPRA2 => addr_read1(2), -- Port B address[2] input bit
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DPRA3 => addr_read1(3), -- Port B address[3] input bit
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DPO => data_out1A(i), -- Port B 1-bit data output
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SPO => no_connect(i) -- Port A 1-bit data output
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);
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--Read port 1 upper 16 registers
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reg_bit1b : RAM16X1D
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port map (
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WCLK => clk, -- Port A write clock input
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WE => weB, -- Port A write enable input
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A0 => addr_write(0), -- Port A address[0] input bit
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A1 => addr_write(1), -- Port A address[1] input bit
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A2 => addr_write(2), -- Port A address[2] input bit
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A3 => addr_write(3), -- Port A address[3] input bit
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D => reg_dest_new(i), -- Port A 1-bit data input
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DPRA0 => addr_read1(0), -- Port B address[0] input bit
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DPRA1 => addr_read1(1), -- Port B address[1] input bit
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DPRA2 => addr_read1(2), -- Port B address[2] input bit
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DPRA3 => addr_read1(3), -- Port B address[3] input bit
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DPO => data_out1B(i), -- Port B 1-bit data output
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SPO => no_connect(32+i) -- Port A 1-bit data output
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);
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--Read port 2 lower 16 registers
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reg_bit2a : RAM16X1D
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port map (
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WCLK => clk, -- Port A write clock input
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WE => weA, -- Port A write enable input
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A0 => addr_write(0), -- Port A address[0] input bit
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A1 => addr_write(1), -- Port A address[1] input bit
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A2 => addr_write(2), -- Port A address[2] input bit
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A3 => addr_write(3), -- Port A address[3] input bit
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D => reg_dest_new(i), -- Port A 1-bit data input
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DPRA0 => addr_read2(0), -- Port B address[0] input bit
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DPRA1 => addr_read2(1), -- Port B address[1] input bit
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DPRA2 => addr_read2(2), -- Port B address[2] input bit
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DPRA3 => addr_read2(3), -- Port B address[3] input bit
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DPO => data_out2A(i), -- Port B 1-bit data output
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SPO => no_connect(64+i) -- Port A 1-bit data output
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);
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--Read port 2 upper 16 registers
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reg_bit2b : RAM16X1D
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port map (
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WCLK => clk, -- Port A write clock input
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WE => weB, -- Port A write enable input
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A0 => addr_write(0), -- Port A address[0] input bit
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A1 => addr_write(1), -- Port A address[1] input bit
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A2 => addr_write(2), -- Port A address[2] input bit
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A3 => addr_write(3), -- Port A address[3] input bit
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D => reg_dest_new(i), -- Port A 1-bit data input
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DPRA0 => addr_read2(0), -- Port B address[0] input bit
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DPRA1 => addr_read2(1), -- Port B address[1] input bit
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DPRA2 => addr_read2(2), -- Port B address[2] input bit
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DPRA3 => addr_read2(3), -- Port B address[3] input bit
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DPO => data_out2B(i), -- Port B 1-bit data output
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SPO => no_connect(96+i) -- Port A 1-bit data output
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);
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end generate; --reg_loop
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data_out1 <= data_out1A when addr_read1(4)='0' else data_out1B;
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data_out2 <= data_out2A when addr_read2(4)='0' else data_out2B;
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end generate; --xilinx_16x1d
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-- Option #4
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-- Altera LPM_RAM_DP
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altera_mem:
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if memory_type = "ALTERA_LPM" generate
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signal clk_delayed : std_logic;
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signal addr_reg : std_logic_vector(4 downto 0);
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signal data_reg : std_logic_vector(31 downto 0);
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signal q1 : std_logic_vector(31 downto 0);
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signal q2 : std_logic_vector(31 downto 0);
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begin
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-- Altera dual port RAMs must have the addresses registered (sampled
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-- at the rising edge). This is very unfortunate.
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-- Therefore, the dual port RAM read clock must delayed so that
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-- the read address signal can be sent from the mem_ctrl block.
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-- This solution also delays the how fast the registers are read so the
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-- maximum clock speed is cut in half (12.5 MHz instead of 25 MHz).
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clk_delayed <= not clk; --Could be delayed by 1/4 clock cycle instead
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dpram_bypass: process(clk, addr_write, reg_dest_new)
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begin
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if rising_edge(clk) and write_enable = '1' then
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addr_reg <= addr_write;
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data_reg <= reg_dest_new;
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end if;
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end process; --dpram_bypass
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-- Bypass dpram if reading what was just written (Altera limitation)
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data_out1 <= q1 when addr_read1 /= addr_reg else data_reg;
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data_out2 <= q2 when addr_read2 /= addr_reg else data_reg;
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lpm_ram_dp_component1 : lpm_ram_dp
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generic map (
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LPM_WIDTH => 32,
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LPM_WIDTHAD => 5,
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--LPM_NUMWORDS => 0,
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LPM_INDATA => "REGISTERED",
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LPM_OUTDATA => "UNREGISTERED",
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LPM_RDADDRESS_CONTROL => "REGISTERED",
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LPM_WRADDRESS_CONTROL => "REGISTERED",
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LPM_FILE => "UNUSED",
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LPM_TYPE => "LPM_RAM_DP",
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USE_EAB => "ON",
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INTENDED_DEVICE_FAMILY => "UNUSED",
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RDEN_USED => "FALSE",
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LPM_HINT => "UNUSED")
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port map (
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RDCLOCK => clk_delayed,
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RDCLKEN => '1',
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RDADDRESS => addr_read1,
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RDEN => '1',
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DATA => reg_dest_new,
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WRADDRESS => addr_write,
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WREN => write_enable,
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WRCLOCK => clk,
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WRCLKEN => '1',
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Q => q1);
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lpm_ram_dp_component2 : lpm_ram_dp
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generic map (
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LPM_WIDTH => 32,
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LPM_WIDTHAD => 5,
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--LPM_NUMWORDS => 0,
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LPM_INDATA => "REGISTERED",
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LPM_OUTDATA => "UNREGISTERED",
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LPM_RDADDRESS_CONTROL => "REGISTERED",
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LPM_WRADDRESS_CONTROL => "REGISTERED",
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LPM_FILE => "UNUSED",
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LPM_TYPE => "LPM_RAM_DP",
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USE_EAB => "ON",
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INTENDED_DEVICE_FAMILY => "UNUSED",
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RDEN_USED => "FALSE",
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LPM_HINT => "UNUSED")
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port map (
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RDCLOCK => clk_delayed,
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RDCLKEN => '1',
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RDADDRESS => addr_read2,
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RDEN => '1',
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DATA => reg_dest_new,
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WRADDRESS => addr_write,
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WREN => write_enable,
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WRCLOCK => clk,
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WRCLKEN => '1',
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Q => q2);
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end generate; --altera_mem
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end; --architecture ram_block
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