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123 lines
3.1 KiB
Verilog
123 lines
3.1 KiB
Verilog
//----------------------------------------------------------------------------
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// Wishbone SRAM controller
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//----------------------------------------------------------------------------
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module wb_sram32 #(
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parameter adr_width = 18,
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parameter latency = 0 // 0 .. 7
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) (
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input clk,
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input reset,
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// Wishbone interface
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input wb_stb_i,
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input wb_cyc_i,
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output reg wb_ack_o,
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input wb_we_i,
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input [31:0] wb_adr_i,
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input [3:0] wb_sel_i,
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input [31:0] wb_dat_i,
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output reg [31:0] wb_dat_o,
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// SRAM connection
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output reg [adr_width-1:0] sram_adr,
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inout [31:0] sram_dat,
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output reg [3:0] sram_be_n, // Byte Enable
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output reg sram_ce_n, // Chip Enable
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output reg sram_oe_n, // Output Enable
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output reg sram_we_n // Write Enable
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);
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//----------------------------------------------------------------------------
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//
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//----------------------------------------------------------------------------
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// Wishbone handling
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wire wb_rd = wb_stb_i & wb_cyc_i & ~wb_we_i & ~wb_ack_o;
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wire wb_wr = wb_stb_i & wb_cyc_i & wb_we_i & ~wb_ack_o;
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// Translate wishbone address to sram address
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wire [adr_width-1:0] adr = wb_adr_i[adr_width+1:2];
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// Tri-State-Driver
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reg [31:0] wdat;
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reg wdat_oe;
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assign sram_dat = wdat_oe ? wdat : 32'bz;
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// Latency countdown
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reg [2:0] lcount;
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//----------------------------------------------------------------------------
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// State Machine
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//----------------------------------------------------------------------------
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parameter s_idle = 0;
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parameter s_read = 1;
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parameter s_write = 2;
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reg [2:0] state;
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always @(posedge clk)
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begin
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if (reset) begin
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state <= s_idle;
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lcount <= 0;
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wb_ack_o <= 0;
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end else begin
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case (state)
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s_idle: begin
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wb_ack_o <= 0;
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if (wb_rd) begin
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sram_ce_n <= 0;
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sram_oe_n <= 0;
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sram_we_n <= 1;
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sram_adr <= adr;
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sram_be_n <= 4'b0000;
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wdat_oe <= 0;
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lcount <= latency;
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state <= s_read;
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end else if (wb_wr) begin
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sram_ce_n <= 0;
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sram_oe_n <= 1;
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sram_we_n <= 0;
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sram_adr <= adr;
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sram_be_n <= ~wb_sel_i;
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wdat <= wb_dat_i;
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wdat_oe <= 1;
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lcount <= latency;
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state <= s_write;
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end else begin
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sram_ce_n <= 1;
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sram_oe_n <= 1;
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sram_we_n <= 1;
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wdat_oe <= 0;
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end
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end
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s_read: begin
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if (lcount != 0) begin
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lcount <= lcount - 1;
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end else begin
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sram_ce_n <= 1;
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sram_oe_n <= 1;
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sram_we_n <= 1;
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wb_dat_o <= sram_dat;
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wb_ack_o <= 1;
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state <= s_idle;
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end
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end
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s_write: begin
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if (lcount != 0) begin
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lcount <= lcount - 1;
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end else begin
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sram_ce_n <= 1;
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sram_oe_n <= 1;
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sram_we_n <= 1;
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wb_ack_o <= 1; // XXX We could acknoledge write XXX
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state <= s_idle; // XXX requests 1 cycle ahead XXX
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end
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end
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endcase
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end
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end
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endmodule
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