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63 lines
1.8 KiB
Verilog
63 lines
1.8 KiB
Verilog
//----------------------------------------------------------------------------
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//
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//----------------------------------------------------------------------------
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`timescale 1 ns / 100 ps
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module system_tb;
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//----------------------------------------------------------------------------
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// Parameter (may differ for physical synthesis)
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//----------------------------------------------------------------------------
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parameter tck = 20; // clock period in ns
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parameter uart_baud_rate = 1152000; // uart baud rate for simulation
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parameter clk_freq = 1000000000 / tck; // Frequenzy in HZ
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//----------------------------------------------------------------------------
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//
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//----------------------------------------------------------------------------
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reg clk;
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reg rst;
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wire led;
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//----------------------------------------------------------------------------
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// UART STUFF (testbench uart, simulating a comm. partner)
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//----------------------------------------------------------------------------
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wire uart_rxd;
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wire uart_txd;
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//----------------------------------------------------------------------------
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// Device Under Test
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//----------------------------------------------------------------------------
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system #(
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.clk_freq( clk_freq ),
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.uart_baud_rate( uart_baud_rate )
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) dut (
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.clk( clk ),
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// Debug
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.rst( rst ),
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.led( led ),
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// Uart
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.uart_rxd( uart_rxd ),
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.uart_txd( uart_txd )
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);
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/* Clocking device */
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initial clk <= 0;
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always #(tck/2) clk <= ~clk;
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/* Simulation setup */
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initial begin
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$dumpfile("system_tb.vcd");
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$dumpvars(-1, dut);
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// reset
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#0 rst <= 1;
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#80 rst <= 0;
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#(tck*10000) $finish;
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end
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endmodule
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