148 lines
6.3 KiB
VHDL
Executable File
148 lines
6.3 KiB
VHDL
Executable File
-------------------------------------------------------------------------------
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-- --
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-- MT32 - Mersenne Twister --
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-- Copyright (C) 2007 HT-LAB --
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-- --
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-- Contact : Use feedback form on the website. --
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-- Web: http://www.ht-lab.com --
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-- --
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-- MT32 files are released under the GNU General Public License. --
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-- --
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-------------------------------------------------------------------------------
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-- --
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-- This library is free software; you can redistribute it and/or --
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-- modify it under the terms of the GNU Lesser General Public --
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-- License as published by the Free Software Foundation; either --
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-- version 2.1 of the License, or (at your option) any later version. --
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-- --
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-- This library is distributed in the hope that it will be useful, --
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --
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-- Lesser General Public License for more details. --
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-- --
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-- Full details of the license can be found in the file "copying.txt". --
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-- --
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-- You should have received a copy of the GNU Lesser General Public --
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-- License along with this library; if not, write to the Free Software --
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
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-- --
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-------------------------------------------------------------------------------
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-- --
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-- Counters, instantiated in top level --
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-------------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_arith.all;
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USE ieee.std_logic_unsigned.all;
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ENTITY counters IS
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GENERIC(
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M : integer := 397;
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N : integer := 623
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);
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PORT(
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clk : IN std_logic;
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resetn : IN std_logic;
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ena : IN std_logic;
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wea : OUT std_logic;
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kk_cnt : OUT std_logic_vector (9 DOWNTO 0);
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km_cnt : OUT std_logic_vector (9 DOWNTO 0);
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kp_cnt : OUT std_logic_vector (9 DOWNTO 0);
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wr_cnt : OUT std_logic_vector (9 DOWNTO 0)
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);
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END counters ;
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--
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ARCHITECTURE rtl OF counters IS
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signal kk_cnt_s : std_logic_vector (9 DOWNTO 0);
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signal km_cnt_s : std_logic_vector (9 DOWNTO 0);
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signal kp_cnt_s : std_logic_vector (9 DOWNTO 0);
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signal wr_cnt_s : std_logic_vector (9 DOWNTO 0);
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BEGIN
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process (clk,resetn)
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begin
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if (resetn='0') then
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wea <= '0';
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elsif (rising_edge(clk)) then
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wea <= ena; -- wea is delayed by 1 clock cycle to
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end if; -- prevent writing outside the dpram address
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end process; -- address range (0..623)
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-------------------------------------------------------------------------------
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-- Write counter which is equal to kk-1
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-- Required to achieve single cycle read/write
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-------------------------------------------------------------------------------
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process (clk,resetn)
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begin
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if (resetn='0') then
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wr_cnt_s <= (others => '1');
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elsif (rising_edge(clk)) then
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if (wr_cnt_s = CONV_STD_LOGIC_VECTOR(N,10)) then
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wr_cnt_s <= (others => '0');
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elsif ena='1' then
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wr_cnt_s <= wr_cnt_s + '1';
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end if;
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end if;
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end process;
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wr_cnt <= wr_cnt_s;
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-------------------------------------------------------------------------------
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-- kk Counter
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-------------------------------------------------------------------------------
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process (clk,resetn)
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begin
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if (resetn='0') then
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kk_cnt_s <= (others => '0');
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elsif (rising_edge(clk)) then
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if (kk_cnt_s = CONV_STD_LOGIC_VECTOR(N,10)) then
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kk_cnt_s <= (others => '0');
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elsif ena='1' then
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kk_cnt_s <= kk_cnt_s + '1';
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end if;
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end if;
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end process;
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kk_cnt <= kk_cnt_s;
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-------------------------------------------------------------------------------
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-- kp Counter
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-------------------------------------------------------------------------------
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process (clk,resetn)
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begin
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if (resetn='0') then
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kp_cnt_s <= "0000000001";
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elsif (rising_edge(clk)) then
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if (kp_cnt_s = CONV_STD_LOGIC_VECTOR(N,10)) then
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kp_cnt_s <= (others => '0');
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elsif ena='1' then
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kp_cnt_s <= kp_cnt_s + '1';
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end if;
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end if;
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end process;
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kp_cnt <= kp_cnt_s;
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-------------------------------------------------------------------------------
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-- km Counter
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-------------------------------------------------------------------------------
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process (clk,resetn)
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begin
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if (resetn='0') then
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km_cnt_s <= CONV_STD_LOGIC_VECTOR(M,10);
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elsif (rising_edge(clk)) then
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if (km_cnt_s = CONV_STD_LOGIC_VECTOR(N,10)) then
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km_cnt_s <= (others => '0');
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elsif ena='1' then
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km_cnt_s <= km_cnt_s + '1';
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end if;
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end if;
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end process;
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km_cnt <= km_cnt_s;
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end architecture rtl;
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