279 lines
7.9 KiB
Verilog
279 lines
7.9 KiB
Verilog
`timescale 1ns / 1ps
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module ehw(clk, sram_data, addr, nwe, ncs, noe, reset, led,
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irq_pin);
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parameter B = (7);
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input clk, addr, nwe, ncs, noe, reset;
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inout [B:0] sram_data;
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output led;
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output irq_pin;
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// synchronize signals
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reg sncs, snwe;
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reg [12:0] buffer_addr;
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reg [B:0] buffer_data;
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wire led;
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// bram-cpu interfaz
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reg we;
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reg w_st=0;
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reg [B:0] wdBus;
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reg [B:0] rdBus;
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wire [12:0] addr;
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reg [7:0] bae;
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// bram-evalfit interfaz
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wire we_eval, en_ev;
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wire [63:0] ev_do;
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wire [63:0] ev_di;
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// Interconnection
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wire [31:0] mt_rnd;
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wire [31:0] reg0;
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wire [31:0] reg1;
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wire [31:0] reg2;
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wire [31:0] reg3;
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wire [31:0] reg4;
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wire [7:0] status;
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wire [15:0] error;
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wire [8:0] evalfit_addr;
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wire en_fit;
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wire [15:0] max_com;
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wire [3:0] max_lev;
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wire [7:0] control;
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reg [7:0] reg_bank [31:0];
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wire enReg;
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wire [4:0] address;
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// Test : LED blinking
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reg [25:0] counter;
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always @(posedge clk) begin
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if (~reset)
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counter <= {25{1'b0}};
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else
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counter <= counter + 1;
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end
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assign led = counter[24];
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// Data Bus direction control
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wire T = ~noe | ncs;
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assign sram_data = T?8'bZ:rdBus;
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// synchronize assignment
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always @(negedge clk)
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begin
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sncs <= ncs;
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snwe <= nwe;
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buffer_data <= sram_data;
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buffer_addr <= addr;
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end
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// write access cpu to bram
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always @(posedge clk)
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if(~reset) {w_st, we, wdBus} <= 0;
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else begin
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wdBus <= buffer_data;
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case (w_st)
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0: begin
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we <= 0;
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if(sncs | snwe) w_st <= 1;
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end
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1: begin
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if(~(sncs | snwe)) begin
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we <= 1;
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w_st <= 0;
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end
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else we <= 0;
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end
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endcase
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end
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// Address Decoder
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// We have 2 memory blocks 1: 512 x 64 bits memory 32kb = 4kB 0000 - 0FFF buffer_addr[12] = 0
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// 2: Register Bank 1000 - 101F buffer_addr[12] = 1
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// SIE has an eight bits data bus, this module generate the required signals to create a 64 bits word.
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always @(buffer_addr)
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begin
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if(~buffer_addr[12]) begin
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case (buffer_addr[2:0])
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0: bae <= 8'h01;
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1: bae <= 8'h02;
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2: bae <= 8'h04;
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3: bae <= 8'h08;
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4: bae <= 8'h10;
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5: bae <= 8'h20;
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6: bae <= 8'h40;
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7: bae <= 8'h80;
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endcase
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end
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else
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bae <= 8'h00;
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end
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wire en1, en2; // enable memory signals
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assign en0 = bae[0] | bae[1] | bae[2] | bae[3];
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assign en1 = bae[4] | bae[5] | bae[6] | bae[7];
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reg[31:0] DIA_Aux;
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always @ (posedge clk) begin
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if (bae[0]) DIA_Aux[7:0] = wdBus[7:0];
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if (bae[1]) DIA_Aux[15:8] = wdBus[7:0];
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if (bae[2]) DIA_Aux[23:16] = wdBus[7:0];
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if (bae[3]) DIA_Aux[31:24] = wdBus[7:0];
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if (bae[4]) DIA_Aux[7:0] = wdBus[7:0];
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if (bae[5]) DIA_Aux[15:8] = wdBus[7:0];
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if (bae[6]) DIA_Aux[23:16] = wdBus[7:0];
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if (bae[7]) DIA_Aux[31:24] = wdBus[7:0];
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end
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reg [2:0] state, nextstate; //FSM for write in 32bit mode to memory
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wire we0, we1;
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wire nreset;
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assign nreset = ~reset;
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parameter S0 = 3'b000;
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parameter S1 = 3'b001;
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parameter S2 = 3'b010;
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always @ (posedge clk, posedge nreset)
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if (nreset) state <= S0;
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else state <= nextstate;
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// next state logic
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always@(*)
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case (state)
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S0:if (bae[3]&we) nextstate = S1;
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else
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if (bae[7]&we) nextstate = S2;
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else nextstate = S0;
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S1: nextstate = S0;
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S2: nextstate = S0;
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default: nextstate = S0;
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endcase
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// output logic
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assign we0 = (state == S1);
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assign we1 = (state == S2);
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// Read control
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reg [7:0] MemDOA;
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wire [63:0] DOA_Aux;
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always @(posedge clk)
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if(~reset)begin
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rdBus = 8'h00;
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end
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else begin
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if(enReg)
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rdBus = reg_bank[address];
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else
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rdBus = MemDOA[7:0];
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end
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// memory output mux
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always @(buffer_addr[2:0])
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case (buffer_addr[2:0])
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0 : MemDOA = DOA_Aux[7:0];
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1 : MemDOA = DOA_Aux[15:8];
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2 : MemDOA = DOA_Aux[23:16];
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3 : MemDOA = DOA_Aux[31:24];
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4 : MemDOA = DOA_Aux[39:32];
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5 : MemDOA = DOA_Aux[47:40];
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6 : MemDOA = DOA_Aux[55:48];
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7 : MemDOA = DOA_Aux[63:56];
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default: MemDOA = 8'h00;
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endcase
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// Store Inputs
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always @(posedge clk)
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begin
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if(enReg) begin
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reg_bank[20] = error[7:0];
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reg_bank[21] = error[15:8];
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reg_bank[22] = status[7:0];
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reg_bank[24] = mt_rnd[7:0];
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reg_bank[25] = mt_rnd[15:8];
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reg_bank[26] = mt_rnd[23:16];
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reg_bank[27] = mt_rnd[31:24];
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end
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end
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assign address[4:0] = buffer_addr[4:0];
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assign enReg = buffer_addr[12];
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assign reg0[7:0] = reg_bank[0];
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assign reg0[15:8] = reg_bank[1];
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assign reg0[23:16] = reg_bank[2];
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assign reg0[31:24] = reg_bank[3];
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assign reg1[7:0] = reg_bank[4];
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assign reg1[15:8] = reg_bank[5];
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assign reg1[23:16] = reg_bank[6];
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assign reg1[31:24] = reg_bank[7];
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assign reg2[7:0] = reg_bank[8];
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assign reg2[15:8] = reg_bank[9];
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assign reg2[23:16] = reg_bank[10];
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assign reg2[31:24] = reg_bank[11];
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assign reg3[7:0] = reg_bank[12];
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assign reg3[15:8] = reg_bank[13];
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assign reg3[23:16] = reg_bank[14];
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assign reg3[31:24] = reg_bank[15];
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assign reg4[7:0] = reg_bank[16];
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assign reg4[15:8] = reg_bank[17];
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assign reg4[23:16] = reg_bank[18];
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assign reg4[31:24] = reg_bank[19];
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assign max_lev = reg_bank[28];
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assign control = reg_bank[29];
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assign max_com[7:0] = reg_bank[30];
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assign max_com[15:8] = reg_bank[31];
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// Write control
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always @(negedge clk)
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if(we & enReg) begin
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case (address)
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0: reg_bank[0] = wdBus;
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1: reg_bank[1] = wdBus;
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2: reg_bank[2] = wdBus;
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3: reg_bank[3] = wdBus;
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4: reg_bank[4] = wdBus;
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5: reg_bank[5] = wdBus;
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6: reg_bank[6] = wdBus;
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7: reg_bank[7] = wdBus;
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8: reg_bank[8] = wdBus;
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9: reg_bank[9] = wdBus;
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10: reg_bank[10] = wdBus;
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11: reg_bank[11] = wdBus;
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12: reg_bank[12] = wdBus;
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13: reg_bank[13] = wdBus;
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14: reg_bank[14] = wdBus;
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15: reg_bank[15] = wdBus;
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16: reg_bank[16] = wdBus;
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17: reg_bank[17] = wdBus;
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18: reg_bank[18] = wdBus;
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19: reg_bank[19] = wdBus;
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28: reg_bank[28] = wdBus;
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29: reg_bank[29] = wdBus;
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30: reg_bank[30] = wdBus;
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31: reg_bank[31] = wdBus;
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endcase
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end
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RAMB16_S36_S36 #(.INIT_00(256'hABCDEF00_00000000_00000000_00000000_00000000_00000000_00000000_76543210) )
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mem0 ( .CLKA(~clk), .ENA(en0), .SSRA(1'b0), .ADDRA(buffer_addr[11:3]), .WEA(we0), .DIA(DIA_Aux[31:0]), .DIPA(0'b0), .DOA(DOA_Aux[31:0]),
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.CLKB(~clk), .ENB(en_ev), .SSRB(1'b0), .ADDRB(evalfit_addr), .WEB(we_eval), .DIB(ev_do[31:0]), .DIPB(0'b0), .DOB(ev_di[31:0]));
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RAMB16_S36_S36 mem1( .CLKA(~clk), .ENA(en1), .SSRA(1'b0), .ADDRA(buffer_addr[11:3]), .WEA(we1), .DIA(DIA_Aux[31:0]), .DIPA(0'b0), .DOA(DOA_Aux[63:32]),
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.CLKB(~clk), .ENB(en_ev),.SSRB(1'b0), .ADDRB(evalfit_addr), .WEB(we_eval), .DIB(ev_do[63:32]), .DIPB(0'b0), .DOB(ev_di[63:32]));
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// evalfit_peripheral
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evalfit_peripheral evalfit( .clk(clk), .reset(~reset), .habilita(control[0]), .maxcombs(max_com), .nivel_max(max_lev),
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.peripheral_mem_in(ev_di), .peripheral_mem_en(en_eval), .peripheral_mem_out(ev_do), .peripheral_mem_we(we_eval),
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.peripheral_mem_addr(evalfit_addr), .evalfit3_estado(status), .errores(error),
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.fin_ack(irq_pin), .reg0_s(reg0), .reg1_s(reg1), .reg2_s(reg2), .reg3_s(reg3), .reg4_s(reg4));
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// MersenneTwister
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mt_mem random( .clk(clk), .ena(1'b1), .resetn(reset), .random(mt_rnd));
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endmodule
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