192 lines
7.0 KiB
VHDL
Executable File
192 lines
7.0 KiB
VHDL
Executable File
-------------------------------------------------------------------------------
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-- --
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-- MT32 - Mersenne Twister --
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-- Copyright (C) 2007 HT-LAB --
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-- --
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-- Contact : Use feedback form on the website. --
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-- Web: http://www.ht-lab.com --
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-- --
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-- MT32 files are released under the GNU General Public License. --
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-- --
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-------------------------------------------------------------------------------
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-- --
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-- This library is free software; you can redistribute it and/or --
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-- modify it under the terms of the GNU Lesser General Public --
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-- License as published by the Free Software Foundation; either --
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-- version 2.1 of the License, or (at your option) any later version. --
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-- --
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-- This library is distributed in the hope that it will be useful, --
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --
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-- Lesser General Public License for more details. --
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-- --
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-- Full details of the license can be found in the file "copying.txt". --
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-- --
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-- You should have received a copy of the GNU Lesser General Public --
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-- License along with this library; if not, write to the Free Software --
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
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-- --
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-------------------------------------------------------------------------------
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-- --
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-- Top Level (Synthesis) --
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-------------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_unsigned.all;
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USE ieee.std_logic_arith.all;
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ENTITY mt_mem IS
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PORT(
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clk : IN std_logic;
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ena : IN std_logic;
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resetn : IN std_logic;
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random : OUT std_logic_vector (31 DOWNTO 0)
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);
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END mt_mem ;
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LIBRARY ieee;
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ARCHITECTURE struct OF mt_mem IS
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-- Architecture declarations
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-- internal signal declarations
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signal kk_cnt : std_logic_vector(9 downto 0);
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signal km_cnt : std_logic_vector(9 downto 0);
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signal kp_cnt : std_logic_vector(9 downto 0);
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signal mt_kk31 : std_logic_vector(0 downto 0);
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signal mt_kk_s : std_logic_vector(31 downto 0);
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signal mt_km : std_logic_vector(31 downto 0);
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signal mt_kp : std_logic_vector(30 downto 0);
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signal wea : std_logic;
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signal wea_s : std_logic_vector(0 downto 0);
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signal wr_cnt : std_logic_vector(9 downto 0);
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signal xor1_s : std_logic_vector(31 downto 0);
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signal xor2_s : std_logic_vector(31 downto 0);
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signal xor3_s : std_logic_vector(31 downto 0);
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signal y_s : std_logic_vector(31 downto 0);
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signal mag01_s : std_logic_vector(31 downto 0);
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-- Component Declarations
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COMPONENT counters
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GENERIC (
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M : integer := 397;
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N : integer := 623
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);
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PORT (
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clk : IN std_logic ;
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resetn : IN std_logic ;
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ena : IN std_logic ;
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wea : OUT std_logic ;
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kk_cnt : OUT std_logic_vector (9 DOWNTO 0);
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km_cnt : OUT std_logic_vector (9 DOWNTO 0);
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kp_cnt : OUT std_logic_vector (9 DOWNTO 0);
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wr_cnt : OUT std_logic_vector (9 DOWNTO 0)
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);
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END COMPONENT;
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COMPONENT dpram624x1
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PORT (
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addra : IN std_logic_VECTOR (9 DOWNTO 0);
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addrb : IN std_logic_VECTOR (9 DOWNTO 0);
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clka : IN std_logic;
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clkb : IN std_logic;
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dina : IN std_logic_VECTOR (0 DOWNTO 0);
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wea : IN std_logic_VECTOR (0 DOWNTO 0);
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doutb : OUT std_logic_VECTOR (0 DOWNTO 0)
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);
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END COMPONENT;
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COMPONENT dpram624x31
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PORT (
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addra : IN std_logic_VECTOR (9 DOWNTO 0);
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addrb : IN std_logic_VECTOR (9 DOWNTO 0);
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clka : IN std_logic;
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clkb : IN std_logic;
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dina : IN std_logic_VECTOR (30 DOWNTO 0);
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wea : IN std_logic_VECTOR (0 DOWNTO 0);
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doutb : OUT std_logic_VECTOR (30 DOWNTO 0)
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);
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END COMPONENT;
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COMPONENT dpram624x32
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PORT (
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addra : IN std_logic_VECTOR (9 DOWNTO 0);
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addrb : IN std_logic_VECTOR (9 DOWNTO 0);
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clka : IN std_logic;
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clkb : IN std_logic;
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dina : IN std_logic_VECTOR (31 DOWNTO 0);
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wea : IN std_logic_VECTOR (0 DOWNTO 0);
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doutb : OUT std_logic_VECTOR (31 DOWNTO 0)
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);
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END COMPONENT;
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BEGIN
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-- Architecture concurrent statements
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-- HDL Embedded Text Block 1 eb1
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-- eb1 1
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wea_s(0) <= wea; -- wonderful VHDL
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-- HDL Embedded Text Block 2 XOR_CHAIN1
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-- eb1 1
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xor1_s <= mt_kk_s XOR ("00000000000"&mt_kk_s(31 downto 11));
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xor2_s <= xor1_s XOR (xor1_s(24 downto 0)&"0000000" AND X"9D2C5680");
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xor3_s <= xor2_s XOR (xor2_s(16 downto 0)&"000000000000000" AND X"EFC60000");
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random <= xor3_s XOR "000000000000000000"&xor3_s(31 downto 18);
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-- HDL Embedded Text Block 3 eb3
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y_s <= mt_kk31(0)&mt_kp(30 downto 0);
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mag01_s <= X"00000000" when y_s(0)='0' else X"9908B0DF";
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mt_kk_s <= mt_km XOR ('0'&y_s(31 downto 1)) XOR mag01_s;
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-- Instance port mappings.
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U_7 : counters
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GENERIC MAP (
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M => 397,
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N => 623
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)
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PORT MAP (
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clk => clk,
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resetn => resetn,
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ena => ena,
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wea => wea,
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kk_cnt => kk_cnt,
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km_cnt => km_cnt,
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kp_cnt => kp_cnt,
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wr_cnt => wr_cnt
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);
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U_0 : dpram624x1
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PORT MAP (
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clka => clk,
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dina => mt_kk_s(31 DOWNTO 31),
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addra => wr_cnt,
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wea => wea_s,
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clkb => clk,
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addrb => kk_cnt,
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doutb => mt_kk31
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);
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U_1 : dpram624x31
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PORT MAP (
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clka => clk,
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dina => mt_kk_s(30 DOWNTO 0),
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addra => wr_cnt,
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wea => wea_s,
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clkb => clk,
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addrb => kp_cnt,
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doutb => mt_kp
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);
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U_2 : dpram624x32
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PORT MAP (
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clka => clk,
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dina => mt_kk_s,
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addra => wr_cnt,
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wea => wea_s,
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clkb => clk,
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addrb => km_cnt,
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doutb => mt_km
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);
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END struct;
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