97 lines
2.2 KiB
Verilog
97 lines
2.2 KiB
Verilog
`timescale 1ns / 1ps
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module reg_bank(clk, reset, en, we, wdBus, rdBus, address, reg0, reg1, reg2, reg3, reg4, regMT, error, status, max_lev, max_com, control);
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input clk, reset, en, we;
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input [7:0] wdBus;
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output [7:0] rdBus;
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input [4:0] address;
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input [31:0] reg0;
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input [31:0] reg1;
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input [31:0] reg2;
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input [31:0] reg3;
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input [31:0] reg4;
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input [31:0] regMT;
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input [16:0] error;
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input [7:0] status;
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output [15:0] max_com;
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output [7:0] max_lev;
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output [7:0] control;
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reg [7:0] reg_bank [31:0];
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reg [7:0] rdBus;
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// Read control
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always @(posedge clk)
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if(reset)
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rdBus = 8'h00;
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else begin
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rdBus = reg_bank[address];
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end
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// Store Inputs
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always @(posedge clk)
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begin
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if(en) begin
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reg_bank[0] = reg0[7:0];
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reg_bank[1] = reg0[15:8];
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reg_bank[2] = reg0[23:16];
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reg_bank[3] = reg0[31:24];
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reg_bank[4] = reg1[7:0];
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reg_bank[5] = reg1[15:8];
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reg_bank[6] = reg1[23:16];
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reg_bank[7] = reg1[31:24];
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reg_bank[8] = reg2[7:0];
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reg_bank[9] = reg2[15:8];
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reg_bank[10] = reg2[23:16];
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reg_bank[11] = reg2[31:24];
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reg_bank[12] = reg3[7:0];
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reg_bank[13] = reg3[15:8];
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reg_bank[14] = reg3[23:16];
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reg_bank[15] = reg3[31:24];
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reg_bank[16] = reg4[7:0];
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reg_bank[17] = reg4[15:8];
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reg_bank[18] = reg4[23:16];
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reg_bank[19] = reg4[31:24];
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reg_bank[20] = error[7:0];
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reg_bank[21] = error[15:8];
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reg_bank[22] = { 4'b0, status};
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// reg_bank[23] = regMT[7:0];
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// reg_bank[24] = regMT[15:8];
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// reg_bank[25] = regMT[23:16];
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// reg_bank[26] = regMT[31:24];
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end
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end
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assign max_com[7:0] = reg_bank[26];
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assign max_com[15:8] = reg_bank[27];
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assign max_lev = reg_bank[28];
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assign control = reg_bank[29];
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// Write control
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always @(negedge clk)
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if(we & en) begin
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case (address)
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27: reg_bank[26] = wdBus;
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28: reg_bank[27] = wdBus;
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29: reg_bank[28] = wdBus;
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30: reg_bank[29] = wdBus;
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endcase
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end
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endmodule
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