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62 lines
2.6 KiB
VHDL
62 lines
2.6 KiB
VHDL
---------------------------------------------------------------------
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-- TITLE: Arithmetic Logic Unit
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-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
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-- DATE CREATED: 2/8/01
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-- FILENAME: alu.vhd
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-- PROJECT: Plasma CPU core
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-- COPYRIGHT: Software placed into the public domain by the author.
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-- Software 'as is' without warranty. Author liable for nothing.
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-- DESCRIPTION:
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-- Implements the ALU.
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---------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use work.mlite_pack.all;
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entity alu is
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generic(alu_type : string := "DEFAULT");
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port(a_in : in std_logic_vector(31 downto 0);
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b_in : in std_logic_vector(31 downto 0);
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alu_function : in alu_function_type;
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c_alu : out std_logic_vector(31 downto 0));
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end; --alu
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architecture logic of alu is
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signal do_add : std_logic;
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signal sum : std_logic_vector(32 downto 0);
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signal less_than : std_logic;
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begin
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do_add <= '1' when alu_function = ALU_ADD else '0';
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sum <= bv_adder(a_in, b_in, do_add);
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less_than <= sum(32) when a_in(31) = b_in(31) or alu_function = ALU_LESS_THAN
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else a_in(31);
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GENERIC_ALU: if alu_type = "DEFAULT" generate
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c_alu <= sum(31 downto 0) when alu_function=ALU_ADD or
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alu_function=ALU_SUBTRACT else
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ZERO(31 downto 1) & less_than when alu_function=ALU_LESS_THAN or
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alu_function=ALU_LESS_THAN_SIGNED else
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a_in or b_in when alu_function=ALU_OR else
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a_in and b_in when alu_function=ALU_AND else
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a_in xor b_in when alu_function=ALU_XOR else
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a_in nor b_in when alu_function=ALU_NOR else
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ZERO;
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end generate;
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AREA_OPTIMIZED_ALU: if alu_type/="DEFAULT" generate
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c_alu <= sum(31 downto 0) when alu_function=ALU_ADD or
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alu_function=ALU_SUBTRACT else (others => 'Z');
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c_alu <= ZERO(31 downto 1) & less_than when alu_function=ALU_LESS_THAN or
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alu_function=ALU_LESS_THAN_SIGNED else
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(others => 'Z');
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c_alu <= a_in or b_in when alu_function=ALU_OR else (others => 'Z');
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c_alu <= a_in and b_in when alu_function=ALU_AND else (others => 'Z');
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c_alu <= a_in xor b_in when alu_function=ALU_XOR else (others => 'Z');
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c_alu <= a_in nor b_in when alu_function=ALU_NOR else (others => 'Z');
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c_alu <= ZERO when alu_function=ALU_NOTHING else (others => 'Z');
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end generate;
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end; --architecture logic
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