Carlos Camargo 1c0db18f4a Adding RXDF TXDF connect them to MAX232, allowing communication between CPU and FPGA via serial port

2010-04-28 18:36:31 -05:00

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SAKC_V1.BOT

Adding RXDF TXDF connect them to MAX232, allowing communication between CPU and FPGA via serial port

2010-04-28 18:36:31 -05:00

SAKC_V1.DRD

Adding RXDF TXDF connect them to MAX232, allowing communication between CPU and FPGA via serial port

2010-04-28 18:36:31 -05:00

SAKC_V1.DTS

Adding RXDF TXDF connect them to MAX232, allowing communication between CPU and FPGA via serial port

2010-04-28 18:36:31 -05:00

SAKC_V1.FAB

Adding RXDF TXDF connect them to MAX232, allowing communication between CPU and FPGA via serial port

2010-04-28 18:36:31 -05:00

SAKC_V1.GTD

Adding RXDF TXDF connect them to MAX232, allowing communication between CPU and FPGA via serial port

2010-04-28 18:36:31 -05:00

SAKC_V1.SMB

Adding RXDF TXDF connect them to MAX232, allowing communication between CPU and FPGA via serial port

2010-04-28 18:36:31 -05:00

SAKC_V1.SMT

Adding RXDF TXDF connect them to MAX232, allowing communication between CPU and FPGA via serial port

2010-04-28 18:36:31 -05:00

SAKC_V1.SPT

Adding RXDF TXDF connect them to MAX232, allowing communication between CPU and FPGA via serial port

2010-04-28 18:36:31 -05:00

SAKC_V1.SSB

Adding RXDF TXDF connect them to MAX232, allowing communication between CPU and FPGA via serial port

2010-04-28 18:36:31 -05:00

SAKC_V1.SST

Adding RXDF TXDF connect them to MAX232, allowing communication between CPU and FPGA via serial port

2010-04-28 18:36:31 -05:00

SAKC_V1.TOP

Adding RXDF TXDF connect them to MAX232, allowing communication between CPU and FPGA via serial port

2010-04-28 18:36:31 -05:00

thruhole.tap

Adding RXDF TXDF connect them to MAX232, allowing communication between CPU and FPGA via serial port

2010-04-28 18:36:31 -05:00