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SAKC_V1.BOT
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Adding RXDF TXDF connect them to MAX232, allowing communication between CPU and FPGA via serial port
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2010-04-28 18:36:31 -05:00 |
SAKC_V1.DRD
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Adding RXDF TXDF connect them to MAX232, allowing communication between CPU and FPGA via serial port
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2010-04-28 18:36:31 -05:00 |
SAKC_V1.DTS
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Adding RXDF TXDF connect them to MAX232, allowing communication between CPU and FPGA via serial port
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2010-04-28 18:36:31 -05:00 |
SAKC_V1.FAB
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Adding RXDF TXDF connect them to MAX232, allowing communication between CPU and FPGA via serial port
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2010-04-28 18:36:31 -05:00 |
SAKC_V1.GTD
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Adding RXDF TXDF connect them to MAX232, allowing communication between CPU and FPGA via serial port
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2010-04-28 18:36:31 -05:00 |
SAKC_V1.SMB
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Adding RXDF TXDF connect them to MAX232, allowing communication between CPU and FPGA via serial port
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2010-04-28 18:36:31 -05:00 |
SAKC_V1.SMT
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Adding RXDF TXDF connect them to MAX232, allowing communication between CPU and FPGA via serial port
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2010-04-28 18:36:31 -05:00 |
SAKC_V1.SPT
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Adding RXDF TXDF connect them to MAX232, allowing communication between CPU and FPGA via serial port
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2010-04-28 18:36:31 -05:00 |
SAKC_V1.SSB
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Adding RXDF TXDF connect them to MAX232, allowing communication between CPU and FPGA via serial port
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2010-04-28 18:36:31 -05:00 |
SAKC_V1.SST
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Adding RXDF TXDF connect them to MAX232, allowing communication between CPU and FPGA via serial port
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2010-04-28 18:36:31 -05:00 |
SAKC_V1.TOP
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Adding RXDF TXDF connect them to MAX232, allowing communication between CPU and FPGA via serial port
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2010-04-28 18:36:31 -05:00 |
thruhole.tap
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Adding RXDF TXDF connect them to MAX232, allowing communication between CPU and FPGA via serial port
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2010-04-28 18:36:31 -05:00 |