mirror of
git://projects.qi-hardware.com/nn-usb-fpga.git
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a7c692d3f0
Adding FPGA sram hdl code and user space code Fixing some errors: LCD's pinout connector is swapped FPGA TDI SIGNAL must be routed to another pin (C14), right now is DQMH Remove R11 Check JZ4725 symbol's component (PORTD is wrong) Adding PB2 and PB3 wiring ADC's vref to external connector Adding power LED Adding CPU Led
67 lines
2.2 KiB
C++
67 lines
2.2 KiB
C++
/* Spartan3 JTAG programming algorithms
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Copyright (C) 2004 Andrew Rogers
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */
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#include "progalgxc3s.h"
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const byte ProgAlgXC3S::JPROGRAM=0x0b;
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const byte ProgAlgXC3S::CFG_IN=0x05;
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const byte ProgAlgXC3S::JSHUTDOWN=0x0d;
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const byte ProgAlgXC3S::JSTART=0x0c;
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const byte ProgAlgXC3S::BYPASS=0x3f;
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ProgAlgXC3S::ProgAlgXC3S(Jtag &j, IOBase &i)
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{
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jtag=&j;
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io=&i;
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}
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int ProgAlgXC3S::program(BitFile &file)
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{
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jtag->shiftIR(&JPROGRAM);
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jtag->shiftIR(&CFG_IN);
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byte init[24];
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jtag->longToByteArray(0xffffffff,&init[0]); // Sync
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jtag->longToByteArray(0x66aa9955,&init[4]); // Sync
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jtag->longToByteArray(0x8001000c,&init[8]); // CMD
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jtag->longToByteArray(0xe0000000,&init[12]); // Clear CRC
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jtag->longToByteArray(0x00000000,&init[16]); // Flush
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jtag->longToByteArray(0x00000000,&init[20]); // Flush
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jtag->shiftDR(init,0,192,32); // Align to 32 bits.
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jtag->shiftIR(&JSHUTDOWN);
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io->cycleTCK(12);
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jtag->shiftIR(&CFG_IN);
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byte hdr[12];
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jtag->longToByteArray(0x8001000c,&hdr[0]); // CMD
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jtag->longToByteArray(0x10000000,&hdr[4]); // Assert GHIGH
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jtag->longToByteArray(0x00000000,&hdr[8]); // Flush
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jtag->shiftDR(hdr,0,96,32,false); // Align to 32 bits and do not goto EXIT1-DR
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jtag->shiftDR(file.getData(),0,file.getLength());
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io->tapTestLogicReset();
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io->setTapState(IOBase::RUN_TEST_IDLE);
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jtag->shiftIR(&JSTART);
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io->cycleTCK(12);
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jtag->shiftIR(&BYPASS); // Don't know why, but without this the FPGA will not reconfigure from Flash when PROG is asserted.
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printf("Done\n");
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}
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