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56 lines
1.0 KiB
Verilog
56 lines
1.0 KiB
Verilog
`timescale 1ns / 1ps
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module blink_TB;
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reg clk;
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reg reset;
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wire led;
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blink uut ( .clk(clk), .reset(reset), .led(led));
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parameter PERIOD = 20;
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parameter real DUTY_CYCLE = 0.5;
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parameter OFFSET = 0;
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parameter TSET = 3;
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parameter THLD = 3;
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parameter NWS = 3;
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event reset_trigger;
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initial begin // Initialize Inputs
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clk = 0; reset = 0;
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end
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initial begin // Process for clk
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#OFFSET;
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forever
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begin
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clk = 1'b0;
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#(PERIOD-(PERIOD*DUTY_CYCLE)) clk = 1'b1;
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#(PERIOD*DUTY_CYCLE);
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end
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end
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initial begin // Reset the system, Start the image capture process
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forever begin
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@ (reset_trigger);
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@ (negedge clk);
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reset = 1;
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@ (negedge clk);
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reset = 0;
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end
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end
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initial begin: TEST_CASE
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$dumpfile("blink_TB.vcd");
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$dumpvars(-1, uut);
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#10 -> reset_trigger;
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#((PERIOD*DUTY_CYCLE)*100) $finish;
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end
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endmodule
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