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94 lines
1.9 KiB
Verilog
94 lines
1.9 KiB
Verilog
/*
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* Milkymist VJ SoC
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* Copyright (C) 2007, 2008, 2009, 2010 Sebastien Bourdeauducq
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, version 3 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/* FIXME: this module does not work. Find out why. */
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module vgafb_asfifo #(
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/* NB: those are fixed in this implementation */
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parameter DATA_WIDTH = 18,
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parameter ADDRESS_WIDTH = 11
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) (
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/* Reading port */
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output [17:0] Data_out,
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output Empty_out,
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input ReadEn_in,
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input RClk,
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/* Writing port */
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input [17:0] Data_in,
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output Full_out,
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input WriteEn_in,
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input WClk,
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input Clear_in
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);
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wire full;
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wire empty;
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FIFO16 #(
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.DATA_WIDTH(9),
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.FIRST_WORD_FALL_THROUGH("TRUE")
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) fifo_lo (
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.ALMOSTEMPTY(),
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.ALMOSTFULL(),
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.DO(Data_out[7:0]),
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.DOP(Data_out[8]),
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.EMPTY(empty),
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.FULL(full),
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.RDCOUNT(),
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.RDERR(),
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.WRCOUNT(),
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.WRERR(),
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.DI(Data_in[7:0]),
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.DIP(Data_in[8]),
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.RDCLK(RClk),
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.RDEN(ReadEn_in & ~empty & ~Clear_in),
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.RST(Clear_in),
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.WRCLK(WClk),
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.WREN(WriteEn_in & ~full & ~Clear_in)
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);
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assign Empty_out = empty;
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assign Full_out = full;
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FIFO16 #(
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.DATA_WIDTH(9),
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.FIRST_WORD_FALL_THROUGH("TRUE")
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) fifo_hi (
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.ALMOSTEMPTY(),
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.ALMOSTFULL(),
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.DO(Data_out[16:9]),
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.DOP(Data_out[17]),
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.EMPTY(),
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.FULL(),
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.RDCOUNT(),
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.RDERR(),
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.WRCOUNT(),
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.WRERR(),
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.DI(Data_in[16:9]),
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.DIP(Data_in[17]),
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.RDCLK(RClk),
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.RDEN(ReadEn_in & ~empty & ~Clear_in),
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.RST(Clear_in),
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.WRCLK(WClk),
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.WREN(WriteEn_in & ~full & ~Clear_in)
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);
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endmodule
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