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44 lines
1.1 KiB
Verilog
44 lines
1.1 KiB
Verilog
//------------------------------------------------------------------
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// Dual port memory (one read and one write port, same width)
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//------------------------------------------------------------------
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module dp_ram #(
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parameter adr_width = 11,
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parameter dat_width = 8
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) (
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// read port a
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input clk_a,
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input [adr_width-1:0] adr_a,
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output reg [dat_width-1:0] dat_a,
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// write port b
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input clk_b,
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input [adr_width-1:0] adr_b,
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input [dat_width-1:0] dat_b,
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input we_b
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);
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parameter depth = (1 << adr_width);
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// actual ram cells
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reg [dat_width-1:0] ram [0:depth-1];
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//------------------------------------------------------------------
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// read port
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//------------------------------------------------------------------
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always @(posedge clk_a)
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begin
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dat_a <= ram[adr_a];
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end
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//------------------------------------------------------------------
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// write port
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//------------------------------------------------------------------
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always @(posedge clk_b)
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begin
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if (we_b) begin
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ram[adr_b] <= dat_b;
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end
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end
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endmodule
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