46 lines
1.1 KiB
Verilog
Executable File
46 lines
1.1 KiB
Verilog
Executable File
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 12:22:40 10/07/2010
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// Design Name:
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// Module Name: kb_ps2
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// Project Name: keyboard
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// Target Devices:
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// Tool versions:
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// Description: controlador de teclado
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//
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// Dependencies: ps2_rx, ps2_tx
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module kb_ps2(
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input wire clk, reset,
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input wire we_ps2,
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inout wire ps2_data, ps2_clk,
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input wire [7:0] din,
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output wire rx_done, tx_done,
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output wire [7:0] dout
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);
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// signal declaration
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wire tx_idle;
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// instantiate ps2 receiver
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ps2_rx ps2_rx_1
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(.clk(clk), .reset(reset), .rx_en(tx_idle),
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.ps2_data(ps2_data), .ps2_clk(ps2_clk),
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.rx_done(rx_done), .dout(dout));
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// instantiate ps2 transmitter
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ps2_tx ps2_tx_1
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(.clk(clk), .reset(reset), .we_ps2(we_ps2),
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.din(din), .ps2_data(ps2_data), .ps2_clk(ps2_clk),
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.tx_idle(tx_idle), .tx_done(tx_done));
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endmodule
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