81 lines
2.2 KiB
Verilog
Executable File
81 lines
2.2 KiB
Verilog
Executable File
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company: UNAL
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// Engineer: Ari Bejarano
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//
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// Create Date: 16:28:50 09/30/2010
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// Design Name: ps2_interface
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// Module Name: ps2_interface
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// Project Name: ps2_interface
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// Target Devices:
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// Tool versions: 2.0
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// Description: ¬¬
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//
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// Dependencies: sync.v, writePulseGenerator.v, kb_ps2
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module ps2_interface(clk, data, addr, nwe, ncs, noe, reset, ps2_data, ps2_clk, irq_kb, led);
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parameter N = 13, M = 8;// M # de lineas de datos, N # de lineas de dirección
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input clk, nwe, ncs, noe, reset;
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input [N-1:0] addr;
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inout [M-1:0] data;
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inout ps2_clk;
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inout ps2_data;
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output irq_kb;
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output led;
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wire sncs;
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wire snwe;
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wire [N-1:0] buffer_addr;
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wire [M-1:0] rdBus;
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wire [M-1:0] wdBus;
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wire we;
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wire rx_done;
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assign led = ps2_clk;
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sync # (.N(13), .M(8))// M # de lineas de datos, N # de lineas de dirección
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sync_U1(.clk(clk),
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.data(data),
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.addr(addr),
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.nwe(nwe),
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.ncs(ncs),
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.noe(noe),
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.rdBus(rdBus),
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.sncs(sncs),
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.snwe(snwe),
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.buffer_addr(buffer_addr),
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.buffer_data(wdBus));
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writePulseGenerator writePulseGenerator_U2 (.clk(clk),
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.snwe(snwe),
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.sncs(sncs),
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.reset(reset),
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.we(we));
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kb_ps2 kb_ps2_U3(.clk(~clk),
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.reset(~reset),
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.we_ps2(we),
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.ps2_data(ps2_data),
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.ps2_clk(ps2_clk),
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.din(wdBus),
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.rx_done(rx_done),
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.tx_done(),
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.dout(rdBus));
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pulse_expander pulse_expander_U4(
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.clk(clk),
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.reset(~reset),
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.pulse_in(rx_done),
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.pulse_out(irq_kb)
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);
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endmodule
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