99 lines
2.2 KiB
Verilog
Executable File
99 lines
2.2 KiB
Verilog
Executable File
`timescale 1ns / 1ps
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module ps2_rx(
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input wire clk, reset,
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input wire ps2_data, ps2_clk, rx_en,
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output reg rx_done,
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output wire [7:0] dout
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);
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//signal declaration
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reg [1:0] state_reg, state_next;
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reg [7:0] filter_reg;
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wire [7:0] filter_next;
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reg f_ps2c_reg;
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wire f_ps2c_next;
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reg [3:0] n_reg, n_next;
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reg [10:0] b_reg, b_next;
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wire fall_edge;
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//====================================================
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// falling - edge generation for ps2_clk
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//====================================================
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always @(posedge clk, posedge reset)
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if (reset)
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begin
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filter_reg <= 0;
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f_ps2c_reg <= 0;
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end
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else
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begin
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filter_reg <= filter_next;
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f_ps2c_reg <= f_ps2c_next;
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end
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assign filter_next = {ps2_clk, filter_reg[7:1]};
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assign f_ps2c_next = (filter_reg==8'b11111111) ? 1'b1 :
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(filter_reg==8'b00000000) ? 1'b0 :
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f_ps2c_reg;
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assign fall_edge = f_ps2c_reg & ~f_ps2c_next;
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//==============================================================
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// FSM
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//==============================================================
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// state & data registers
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always @(posedge clk, posedge reset)
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if(reset)
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begin
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state_reg <= 1;
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n_reg <= 0;
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b_reg <= 0;
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end
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else
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begin
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state_reg <= state_next;
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n_reg <= n_next;
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b_reg <= b_next;
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end
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// next state logic
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always @(*)
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begin
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state_next = state_reg;
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n_next = n_reg;
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b_next = b_reg;
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rx_done = 1'b0;
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case(state_reg)
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1:
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if(fall_edge & rx_en)
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begin
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//shift in start bit
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b_next = {ps2_data, b_reg[10:1]};
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n_next = 4'b1001;
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state_next = 2;
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end
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2: // 8 data + 1 parity + 1 stop
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begin
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if(fall_edge)
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begin
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b_next = {ps2_data, b_reg[10:1]};
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if(n_reg==0)
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state_next = 3;
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else
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n_next = n_reg-1;
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end
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end
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3: // 1 extra clock to complete the last shift
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begin
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state_next = 1;
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rx_done = 1'b1;
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end
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default: state_next = 1;
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endcase
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end
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//output
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assign dout = b_reg[8:1]; //data bits
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endmodule
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