166 lines
4.1 KiB
Verilog
Executable File
166 lines
4.1 KiB
Verilog
Executable File
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 11:52:20 10/07/2010
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// Design Name:
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// Module Name: ps2_tx
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// Project Name: keyboard
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// Target Devices:
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// Tool versions:
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// Description: transmisor de teclado ps2
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module ps2_tx
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(
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input wire clk, reset,
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input wire we_ps2,
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input wire [7:0] din,
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inout wire ps2_data, ps2_clk,
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output reg tx_idle, tx_done
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);
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// symbolic state declaration
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localparam [2:0]
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idle = 3'b000,
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rts = 3'b001,
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start = 3'b010,
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data = 3'b011,
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stop = 3'b100;
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// signal declaration
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reg [2:0] state_reg, state_next;
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reg [7:0] filter_reg;
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wire [7:0] filter_next;
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reg f_ps2c_reg;
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wire f_ps2c_next;
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reg [3:0] n_reg, n_next;
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reg [8:0] b_reg, b_next;
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reg [12:0] c_reg, c_next;
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wire par, fall_edge;
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reg ps2c_out, ps2d_out;
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reg tri_c, tri_d;
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//=================================================
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// falling-edge generation for ps2_clk
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//=================================================
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always @(posedge clk, posedge reset)
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if (reset)
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begin
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filter_reg <= 0;
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f_ps2c_reg <= 0;
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end
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else
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begin
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filter_reg <= filter_next;
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f_ps2c_reg <= f_ps2c_next;
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end
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assign filter_next = {ps2_clk, filter_reg[7:1]};
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assign f_ps2c_next = (filter_reg==8'b11111111) ? 1'b1 :
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(filter_reg==8'b00000000) ? 1'b0 :
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f_ps2c_reg;
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assign fall_edge = f_ps2c_reg & ~f_ps2c_next;
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//=================================================
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// FSM
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//=================================================
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// state & data registers
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always @(posedge clk, posedge reset)
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if (reset)
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begin
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state_reg <= idle;
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c_reg <= 0;
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n_reg <= 0;
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b_reg <= 0;
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end
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else
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begin
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state_reg <= state_next;
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c_reg <= c_next;
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n_reg <= n_next;
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b_reg <= b_next;
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end
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// odd parity bit
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assign par = ~(^din);
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// FSM next-state logic
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always @*
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begin
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state_next = state_reg;
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c_next = c_reg;
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n_next = n_reg;
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b_next = b_reg;
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tx_done = 1'b0;
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ps2c_out = 1'bz;
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ps2d_out = 1'bz;
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tri_c = 1'b0;
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tri_d = 1'b0;
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tx_idle = 1'b0;
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case (state_reg)
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idle:
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begin
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tx_idle = 1'b1;
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if (we_ps2)
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begin
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b_next = {par, din};
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c_next = 13'h1fff; // 2^13-1
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state_next = rts;
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end
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end
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rts: // request to send
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begin
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ps2c_out = 1'b0;
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tri_c = 1'b1;
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c_next = c_reg - 1;
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if (c_reg==0)
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state_next = start;
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end
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start: // assert start bit
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begin
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ps2d_out = 1'b0;
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tri_d = 1'b1;
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if (fall_edge)
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begin
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n_next = 4'h8;
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state_next = data;
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end
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end
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data: // 8 data + 1 parity
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begin
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ps2d_out = (b_reg[0])? 1'bz : 1'b0;
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tri_d = 1'b1;
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if (fall_edge)
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begin
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b_next = {1'b0, b_reg[8:1]};
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if (n_reg == 0)
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state_next = stop;
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else
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n_next = n_reg - 1;
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end
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end
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stop: // assume floating high for ps2_data
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if (fall_edge)
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begin
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state_next = idle;
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tx_done = 1'b1;
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end
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endcase
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end
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// tri-state buffers
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assign ps2_clk = (tri_c) ? ps2c_out : 1'bz;
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assign ps2_data = (tri_d) ? ps2d_out : 1'bz;
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endmodule
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