58 lines
1.2 KiB
Verilog
Executable File
58 lines
1.2 KiB
Verilog
Executable File
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company: U.N
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// Engineer: Ari Andrés Bejarano H.
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//
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// Create Date: 07:19:56 10/15/2010
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// Design Name:
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// Module Name: pulse_expander
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// Project Name:
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// Target Devices:
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// Tool versions:
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// Description: expande pulse_out = (pulse_in) + (num * pulses of clk)
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module pulse_expander(
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input clk,
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input reset,
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input pulse_in,
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output reg pulse_out
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);
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parameter num = 5000;
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reg [24:0] cnt;
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reg flag;
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always@(posedge clk)begin
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if(reset)
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begin
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cnt <= 0;
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pulse_out <= 0;
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flag <= 0;
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end
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else
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if(pulse_in || flag)
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if(cnt < num)
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begin
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cnt <= cnt+1;
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pulse_out <= 1;
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flag <= 1;
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end
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else
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begin
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cnt <= 0;
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pulse_out <= 0;
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flag <= 0;
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end
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end
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endmodule
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