83 lines
1.5 KiB
Verilog
Executable File
83 lines
1.5 KiB
Verilog
Executable File
`timescale 1ns / 1ps
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////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 08:01:22 10/15/2010
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// Design Name: pulse_expander
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// Module Name: /home/ari/Xilinx_Projects/keyboard/pulse_expander_TF.v
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// Project Name: keyboard
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// Target Device:
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// Tool versions:
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// Description:
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//
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// Verilog Test Fixture created by ISE for module: pulse_expander
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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////////////////////////////////////////////////////////////////////////////////
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module pulse_expander_TF;
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// Inputs
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reg clk;
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reg reset;
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reg pulse_in;
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// Outputs
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wire pulse_out;
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// Instantiate the Unit Under Test (UUT)
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pulse_expander uut (
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.clk(clk),
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.reset(reset),
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.pulse_in(pulse_in),
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.pulse_out(pulse_out)
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);
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initial begin
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// Initialize Inputs
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clk = 0;
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reset = 0;
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pulse_in = 0;
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// Wait 100 ns for global reset to finish
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#100;
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// Add stimulus here
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reset = 1;
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#100;
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reset = 0;
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#100;
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pulse_in = 1;
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#20;
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pulse_in = 0;
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#400;
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pulse_in = 1;
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#20;
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pulse_in = 0;
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end
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always
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#10 clk=!clk;
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initial begin
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$dumpfile ("pulse_expander_TF.vcd");
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$dumpvars;
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end
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initial begin
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$display("\t\ttime,\tclk,\treset,\tpulse_in,\tpulse_out");
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$monitor("%d,\t%b,\t%b,\t%b,\t%d",$time, clk,reset,pulse_in,pulse_out);
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end
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initial
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#2000 $finish;
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endmodule
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