691 lines
30 KiB
Plaintext
691 lines
30 KiB
Plaintext
Release 10.1.03 - xst K.39 (lin)
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Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved.
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-->
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PMSPEC -- Overriding Xilinx file </opt/cad/Xilinx/10.1/ISE/spartan3/data/spartan3.acd> with local file </opt/cad/Xilinx/10.1/ISE/spartan3/data/spartan3.acd>
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TABLE OF CONTENTS
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1) Synthesis Options Summary
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2) HDL Compilation
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3) Design Hierarchy Analysis
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4) HDL Analysis
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5) HDL Synthesis
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5.1) HDL Synthesis Report
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6) Advanced HDL Synthesis
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6.1) Advanced HDL Synthesis Report
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7) Low Level Synthesis
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8) Partition Report
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9) Final Report
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9.1) Device utilization summary
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9.2) Partition Resource Summary
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9.3) TIMING REPORT
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=========================================================================
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* Synthesis Options Summary *
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=========================================================================
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---- Source Parameters
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Input File Name : "project.src"
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Input Format : mixed
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---- Target Parameters
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Target Device : xc3s500e-VQ100-4
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Output File Name : "project.ngc"
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Output Format : NGC
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---- Source Options
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Top Module Name : uart_peripheral
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---- General Options
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Optimization Goal : Area
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Optimization Effort : 1
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RTL Output : yes
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=========================================================================
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=========================================================================
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* HDL Compilation *
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=========================================================================
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Compiling verilog file "../uart_peripheral.v" in library work
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Compiling verilog file "../uart.v" in library work
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Module <uart_peripheral> compiled
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Module <UART> compiled
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Module <pc_buffrx_pc> compiled
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Module <pc_bufftx> compiled
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Module <pc_ctrl_rx> compiled
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Module <pc_ctrl_tx_pc> compiled
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Module <pc_dato_rdy> compiled
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Module <pc_div27> compiled
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Module <pc_div16> compiled
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Module <pc_div_ms> compiled
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Module <pc_ier> compiled
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Module <pc_if_arm_pc> compiled
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Module <pc_ifrxd> compiled
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Module <pc_isr> compiled
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Module <pc_lcr> compiled
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Module <pc_muestreo> compiled
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Module <pc_pulso> compiled
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No errors in compilation
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Analysis of file <"project.src"> succeeded.
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=========================================================================
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* Design Hierarchy Analysis *
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=========================================================================
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Analyzing hierarchy for module <uart_peripheral> in library <work> with parameters.
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B = "00000000000000000000000000000111"
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Analyzing hierarchy for module <UART> in library <work>.
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Analyzing hierarchy for module <pc_if_arm_pc> in library <work>.
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Analyzing hierarchy for module <pc_div27> in library <work>.
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Analyzing hierarchy for module <pc_div_ms> in library <work>.
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Analyzing hierarchy for module <pc_pulso> in library <work>.
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Analyzing hierarchy for module <pc_div16> in library <work>.
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Analyzing hierarchy for module <pc_ifrxd> in library <work>.
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Analyzing hierarchy for module <pc_muestreo> in library <work>.
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Analyzing hierarchy for module <pc_buffrx_pc> in library <work>.
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Analyzing hierarchy for module <pc_ctrl_rx> in library <work>.
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Analyzing hierarchy for module <pc_dato_rdy> in library <work>.
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Analyzing hierarchy for module <pc_bufftx> in library <work>.
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Analyzing hierarchy for module <pc_ctrl_tx_pc> in library <work>.
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Analyzing hierarchy for module <pc_ier> in library <work>.
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Analyzing hierarchy for module <pc_lcr> in library <work>.
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Analyzing hierarchy for module <pc_isr> in library <work>.
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=========================================================================
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* HDL Analysis *
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=========================================================================
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Analyzing top module <uart_peripheral>.
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B = 32'sb00000000000000000000000000000111
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WARNING:Xst:852 - "../uart_peripheral.v" line 63: Unconnected input port 'CD' of instance 'UART' is tied to GND.
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WARNING:Xst:852 - "../uart_peripheral.v" line 63: Unconnected input port 'RI' of instance 'UART' is tied to GND.
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WARNING:Xst:852 - "../uart_peripheral.v" line 63: Unconnected input port 'DSR' of instance 'UART' is tied to GND.
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WARNING:Xst:852 - "../uart_peripheral.v" line 63: Unconnected input port 'CTS' of instance 'UART' is tied to GND.
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Module <uart_peripheral> is correct for synthesis.
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Analyzing module <UART> in library <work>.
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Module <UART> is correct for synthesis.
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Analyzing module <pc_if_arm_pc> in library <work>.
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Module <pc_if_arm_pc> is correct for synthesis.
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Analyzing module <pc_div27> in library <work>.
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Module <pc_div27> is correct for synthesis.
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Analyzing module <pc_div_ms> in library <work>.
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Module <pc_div_ms> is correct for synthesis.
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Analyzing module <pc_pulso> in library <work>.
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Module <pc_pulso> is correct for synthesis.
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Analyzing module <pc_div16> in library <work>.
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Module <pc_div16> is correct for synthesis.
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Analyzing module <pc_ifrxd> in library <work>.
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Module <pc_ifrxd> is correct for synthesis.
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Analyzing module <pc_muestreo> in library <work>.
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Module <pc_muestreo> is correct for synthesis.
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Analyzing module <pc_buffrx_pc> in library <work>.
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Module <pc_buffrx_pc> is correct for synthesis.
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Analyzing module <pc_ctrl_rx> in library <work>.
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Module <pc_ctrl_rx> is correct for synthesis.
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Analyzing module <pc_dato_rdy> in library <work>.
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Module <pc_dato_rdy> is correct for synthesis.
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Analyzing module <pc_bufftx> in library <work>.
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Module <pc_bufftx> is correct for synthesis.
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Analyzing module <pc_ctrl_tx_pc> in library <work>.
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Module <pc_ctrl_tx_pc> is correct for synthesis.
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Analyzing module <pc_ier> in library <work>.
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Module <pc_ier> is correct for synthesis.
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Analyzing module <pc_lcr> in library <work>.
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Module <pc_lcr> is correct for synthesis.
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Analyzing module <pc_isr> in library <work>.
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Module <pc_isr> is correct for synthesis.
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=========================================================================
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* HDL Synthesis *
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=========================================================================
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Performing bidirectional port resolution...
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INFO:Xst:2679 - Register <buftx<10>> in unit <pc_bufftx> has a constant value of 1 during circuit operation. The register is replaced by logic.
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Synthesizing Unit <pc_if_arm_pc>.
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Related source file is "../uart.v".
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WARNING:Xst:647 - Input <CLK> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
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WARNING:Xst:647 - Input <reset> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
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WARNING:Xst:647 - Input <data_in> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
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WARNING:Xst:1780 - Signal <dato_tx> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
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Unit <pc_if_arm_pc> synthesized.
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Synthesizing Unit <pc_div27>.
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Related source file is "../uart.v".
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Found 6-bit up counter for signal <div27>.
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Summary:
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inferred 1 Counter(s).
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Unit <pc_div27> synthesized.
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Synthesizing Unit <pc_div_ms>.
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Related source file is "../uart.v".
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Found 1-bit register for signal <clk_out>.
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Found 16-bit register for signal <div>.
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Found 16-bit adder for signal <div$addsub0000> created at line 581.
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Found 16-bit comparator equal for signal <div$cmp_eq0000> created at line 574.
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Found 16-bit register for signal <k_div>.
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Summary:
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inferred 33 D-type flip-flop(s).
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inferred 1 Adder/Subtractor(s).
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inferred 1 Comparator(s).
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Unit <pc_div_ms> synthesized.
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Synthesizing Unit <pc_pulso>.
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Related source file is "../uart.v".
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Found 1-bit register for signal <dff>.
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Summary:
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inferred 1 D-type flip-flop(s).
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Unit <pc_pulso> synthesized.
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Synthesizing Unit <pc_div16>.
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Related source file is "../uart.v".
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Found 4-bit up counter for signal <div16>.
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Summary:
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inferred 1 Counter(s).
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Unit <pc_div16> synthesized.
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Synthesizing Unit <pc_ifrxd>.
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Related source file is "../uart.v".
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Found 3-bit register for signal <ifrxd>.
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Found 1-bit xor2 for signal <ifrxd_2$xor0000> created at line 967.
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Found 1-bit xor2 for signal <ifrxd_2$xor0001> created at line 967.
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Summary:
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inferred 3 D-type flip-flop(s).
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Unit <pc_ifrxd> synthesized.
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Synthesizing Unit <pc_muestreo>.
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Related source file is "../uart.v".
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Found 1-bit register for signal <sample>.
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Found 4-bit up counter for signal <cont_m>.
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Found 1-bit register for signal <flag_rx>.
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Summary:
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inferred 1 Counter(s).
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inferred 2 D-type flip-flop(s).
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Unit <pc_muestreo> synthesized.
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Synthesizing Unit <pc_buffrx_pc>.
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Related source file is "../uart.v".
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Found 1-bit register for signal <err_paridad>.
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Found 8-bit register for signal <datorx>.
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Found 1-bit register for signal <err_frame>.
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Found 10-bit register for signal <bufrx>.
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Found 1-bit xor9 for signal <iparity>.
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Summary:
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inferred 20 D-type flip-flop(s).
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inferred 1 Xor(s).
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Unit <pc_buffrx_pc> synthesized.
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Synthesizing Unit <pc_ctrl_rx>.
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Related source file is "../uart.v".
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Found 1-bit register for signal <rx_lleno>.
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Found 4-bit up counter for signal <cont_rx>.
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Summary:
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inferred 1 Counter(s).
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inferred 1 D-type flip-flop(s).
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Unit <pc_ctrl_rx> synthesized.
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Synthesizing Unit <pc_dato_rdy>.
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Related source file is "../uart.v".
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Found 1-bit register for signal <dato_rdy>.
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Found 1-bit register for signal <err_overrun>.
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Summary:
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inferred 2 D-type flip-flop(s).
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Unit <pc_dato_rdy> synthesized.
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Synthesizing Unit <pc_bufftx>.
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Related source file is "../uart.v".
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Found 10-bit register for signal <buftx<9:0>>.
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Found 8-bit register for signal <dato_tx>.
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Found 1-bit xor8 for signal <iparity>.
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Summary:
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inferred 18 D-type flip-flop(s).
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inferred 1 Xor(s).
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Unit <pc_bufftx> synthesized.
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Synthesizing Unit <pc_ctrl_tx_pc>.
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Related source file is "../uart.v".
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Found 1-bit register for signal <tx_empty>.
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Found 4-bit up counter for signal <cont_tx>.
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Found 1-bit register for signal <tx_on>.
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Summary:
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inferred 1 Counter(s).
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inferred 2 D-type flip-flop(s).
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Unit <pc_ctrl_tx_pc> synthesized.
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Synthesizing Unit <pc_ier>.
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Related source file is "../uart.v".
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WARNING:Xst:647 - Input <data_in<7:4>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
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Found 4-bit register for signal <IER>.
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Summary:
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inferred 4 D-type flip-flop(s).
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Unit <pc_ier> synthesized.
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Synthesizing Unit <pc_lcr>.
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Related source file is "../uart.v".
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Found 8-bit register for signal <LCR>.
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Summary:
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inferred 8 D-type flip-flop(s).
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Unit <pc_lcr> synthesized.
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Synthesizing Unit <pc_isr>.
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Related source file is "../uart.v".
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WARNING:Xst:647 - Input <IER<2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
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WARNING:Xst:646 - Signal <err_overrunm> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
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Found 4-bit register for signal <ISR>.
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Found 1-bit register for signal <aux1>.
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Found 1-bit register for signal <carga_ISRd>.
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Found 1-bit register for signal <mask_dato_rdy>.
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Found 1-bit register for signal <mask_err_overrun>.
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Found 1-bit register for signal <mask_error>.
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Found 1-bit register for signal <mask_modem_int>.
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Found 1-bit register for signal <mask_tx_empty>.
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Summary:
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inferred 11 D-type flip-flop(s).
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Unit <pc_isr> synthesized.
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Synthesizing Unit <UART>.
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Related source file is "../uart.v".
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WARNING:Xst:647 - Input <CD> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
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WARNING:Xst:1305 - Output <RTS> is never assigned. Tied to value 0.
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WARNING:Xst:647 - Input <CTS> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
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WARNING:Xst:647 - Input <DSR> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
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WARNING:Xst:1305 - Output <DTR> is never assigned. Tied to value 0.
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WARNING:Xst:647 - Input <RI> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
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WARNING:Xst:653 - Signal <modem_int> is used but never assigned. This sourceless signal will be automatically connected to value 0.
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WARNING:Xst:653 - Signal <modem> is used but never assigned. This sourceless signal will be automatically connected to value 00000000.
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WARNING:Xst:1780 - Signal <error> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
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WARNING:Xst:1780 - Signal <dato_tx> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
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WARNING:Xst:1780 - Signal <carga_div> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
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WARNING:Xst:646 - Signal <carga_MSR> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
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WARNING:Xst:646 - Signal <carga_MCR> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
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WARNING:Xst:646 - Signal <WordLength> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
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WARNING:Xst:646 - Signal <Stop> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
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WARNING:Xst:646 - Signal <Break> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
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Unit <UART> synthesized.
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Synthesizing Unit <uart_peripheral>.
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Related source file is "../uart_peripheral.v".
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WARNING:Xst:647 - Input <RxD2> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
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WARNING:Xst:1306 - Output <TxD2> is never assigned.
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WARNING:Xst:646 - Signal <out> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
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WARNING:Xst:646 - Signal <buffer_addr<12:3>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
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WARNING:Xst:1780 - Signal <RD> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
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WARNING:Xst:1780 - Signal <ISRC_LP> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
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Found 8-bit tristate buffer for signal <sram_data>.
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Found 13-bit register for signal <buffer_addr>.
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Found 8-bit register for signal <buffer_data>.
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Found 24-bit up counter for signal <counter>.
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Found 1-bit register for signal <sncs>.
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Found 1-bit register for signal <snwe>.
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Found 1-bit register for signal <w_st>.
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Found 8-bit register for signal <wdBus>.
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Found 1-bit register for signal <we>.
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Summary:
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inferred 1 Counter(s).
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inferred 33 D-type flip-flop(s).
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inferred 8 Tristate(s).
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Unit <uart_peripheral> synthesized.
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=========================================================================
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HDL Synthesis Report
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Macro Statistics
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# Adders/Subtractors : 1
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16-bit adder : 1
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# Counters : 6
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24-bit up counter : 1
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4-bit up counter : 4
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6-bit up counter : 1
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# Registers : 71
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1-bit register : 62
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13-bit register : 1
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16-bit register : 1
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4-bit register : 2
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8-bit register : 5
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# Comparators : 1
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16-bit comparator equal : 1
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# Tristates : 1
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8-bit tristate buffer : 1
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# Xors : 4
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1-bit xor2 : 2
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1-bit xor8 : 1
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1-bit xor9 : 1
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=========================================================================
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=========================================================================
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* Advanced HDL Synthesis *
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=========================================================================
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Loading device for application Rf_Device from file '3s500e.nph' in environment /opt/cad/Xilinx/10.1/ISE:/opt/cad/Xilinx/10.1/ISE/.
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WARNING:Xst:1710 - FF/Latch <ISR_3> (without init value) has a constant value of 0 in block <pc_isr>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:2677 - Node <buffer_addr_3> of sequential type is unconnected in block <uart_peripheral>.
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WARNING:Xst:2677 - Node <buffer_addr_4> of sequential type is unconnected in block <uart_peripheral>.
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WARNING:Xst:2677 - Node <buffer_addr_5> of sequential type is unconnected in block <uart_peripheral>.
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WARNING:Xst:2677 - Node <buffer_addr_6> of sequential type is unconnected in block <uart_peripheral>.
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WARNING:Xst:2677 - Node <buffer_addr_7> of sequential type is unconnected in block <uart_peripheral>.
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WARNING:Xst:2677 - Node <buffer_addr_8> of sequential type is unconnected in block <uart_peripheral>.
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WARNING:Xst:2677 - Node <buffer_addr_9> of sequential type is unconnected in block <uart_peripheral>.
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WARNING:Xst:2677 - Node <buffer_addr_10> of sequential type is unconnected in block <uart_peripheral>.
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WARNING:Xst:2677 - Node <buffer_addr_11> of sequential type is unconnected in block <uart_peripheral>.
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WARNING:Xst:2677 - Node <buffer_addr_12> of sequential type is unconnected in block <uart_peripheral>.
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WARNING:Xst:2677 - Node <IER_3> of sequential type is unconnected in block <ier1>.
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WARNING:Xst:2677 - Node <mask_modem_int> of sequential type is unconnected in block <isr1>.
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=========================================================================
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Advanced HDL Synthesis Report
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Macro Statistics
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# Adders/Subtractors : 1
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16-bit adder : 1
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# Counters : 6
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24-bit up counter : 1
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4-bit up counter : 4
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6-bit up counter : 1
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# Registers : 128
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Flip-Flops : 128
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# Comparators : 1
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16-bit comparator equal : 1
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# Xors : 4
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1-bit xor2 : 2
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1-bit xor8 : 1
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1-bit xor9 : 1
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=========================================================================
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=========================================================================
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* Low Level Synthesis *
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=========================================================================
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WARNING:Xst:2677 - Node <mask_modem_int> of sequential type is unconnected in block <pc_isr>.
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Optimizing unit <uart_peripheral> ...
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Optimizing unit <pc_div_ms> ...
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Optimizing unit <pc_buffrx_pc> ...
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Optimizing unit <pc_bufftx> ...
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Optimizing unit <pc_isr> ...
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WARNING:Xst:2677 - Node <UART/ier1/IER_3> of sequential type is unconnected in block <uart_peripheral>.
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Mapping all equations...
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Building and optimizing final netlist ...
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FlipFlop counter_23 has been replicated 1 time(s) to handle iob=true attribute.
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Final Macro Processing ...
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=========================================================================
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Final Register Report
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Macro Statistics
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# Registers : 173
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Flip-Flops : 173
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=========================================================================
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=========================================================================
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* Partition Report *
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=========================================================================
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Partition Implementation Status
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-------------------------------
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No Partitions were found in this design.
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-------------------------------
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=========================================================================
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* Final Report *
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=========================================================================
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Final Results
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RTL Top Level Output File Name : project.ngr
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Top Level Output File Name : project.ngc
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Output Format : NGC
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Optimization Goal : Area
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Keep Hierarchy : no
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Design Statistics
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# IOs : 22
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Cell Usage :
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# BELS : 278
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# GND : 1
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# INV : 9
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# LUT1 : 38
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# LUT2 : 10
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# LUT3 : 48
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# LUT4 : 78
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# MUXCY : 46
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# MUXF5 : 7
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# VCC : 1
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# XORCY : 40
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# FlipFlops/Latches : 173
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# FD : 3
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# FD_1 : 13
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# FDC : 10
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# FDCE : 80
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# FDE : 1
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# FDP : 1
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# FDPE : 14
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# FDR : 36
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# FDRE : 12
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# FDSE : 3
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# Clock Buffers : 1
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# BUFGP : 1
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# IO Buffers : 19
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# IBUF : 8
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# IOBUF : 8
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# OBUF : 3
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=========================================================================
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Device utilization summary:
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---------------------------
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Selected Device : 3s500evq100-4
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Number of Slices: 114 out of 4656 2%
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Number of Slice Flip Flops: 158 out of 9312 1%
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Number of 4 input LUTs: 183 out of 9312 1%
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Number of IOs: 22
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Number of bonded IOBs: 20 out of 66 30%
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IOB Flip Flops: 15
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Number of GCLKs: 1 out of 24 4%
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---------------------------
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Partition Resource Summary:
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---------------------------
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No Partitions were found in this design.
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---------------------------
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=========================================================================
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TIMING REPORT
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NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
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FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
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GENERATED AFTER PLACE-and-ROUTE.
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Clock Information:
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------------------
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-----------------------------------+------------------------+-------+
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Clock Signal | Clock buffer(FF name) | Load |
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-----------------------------------+------------------------+-------+
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clk | BUFGP | 173 |
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-----------------------------------+------------------------+-------+
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Asynchronous Control Signals Information:
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----------------------------------------
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-----------------------------------+---------------------------+-------+
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Control Signal | Buffer(FF name) | Load |
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-----------------------------------+---------------------------+-------+
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reset_inv(reset_inv1_INV_0:O) | NONE(UART/bufftx1/buftx_9)| 105 |
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-----------------------------------+---------------------------+-------+
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Timing Summary:
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---------------
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Speed Grade: -4
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Minimum period: 13.338ns (Maximum Frequency: 74.974MHz)
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Minimum input arrival time before clock: 4.803ns
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Maximum output required time after clock: 9.916ns
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Maximum combinational path delay: 6.573ns
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Timing Detail:
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--------------
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All values displayed in nanoseconds (ns)
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=========================================================================
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Timing constraint: Default period analysis for Clock 'clk'
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Clock period: 13.338ns (frequency: 74.974MHz)
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Total number of paths / destination ports: 2891 / 269
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-------------------------------------------------------------------------
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Delay: 6.669ns (Levels of Logic = 3)
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Source: buffer_addr_1 (FF)
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Destination: UART/div_ms1/div_15 (FF)
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Source Clock: clk falling
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Destination Clock: clk rising
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Data Path: buffer_addr_1 to UART/div_ms1/div_15
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Gate Net
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Cell:in->out fanout Delay Delay Logical Name (Net Name)
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---------------------------------------- ------------
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FD_1:C->Q 13 0.591 0.987 buffer_addr_1 (buffer_addr_1)
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LUT4:I3->O 3 0.704 0.566 UART/if_arm1/data_out_cmp_eq00001 (UART/if_arm1/data_out_cmp_eq0000)
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LUT3:I2->O 9 0.704 0.824 UART/if_arm1/carga_div_low1 (UART/carga_div_low)
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LUT4:I3->O 16 0.704 1.034 UART/div_ms1/div_not00021 (UART/div_ms1/div_not0002)
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FDCE:CE 0.555 UART/div_ms1/div_0
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----------------------------------------
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Total 6.669ns (3.258ns logic, 3.411ns route)
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(48.9% logic, 51.1% route)
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=========================================================================
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Timing constraint: Default OFFSET IN BEFORE for Clock 'clk'
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Total number of paths / destination ports: 69 / 69
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-------------------------------------------------------------------------
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Offset: 4.803ns (Levels of Logic = 2)
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Source: reset (PAD)
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Destination: w_st (FF)
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Destination Clock: clk rising
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Data Path: reset to w_st
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Gate Net
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Cell:in->out fanout Delay Delay Logical Name (Net Name)
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---------------------------------------- ------------
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IBUF:I->O 6 1.218 0.669 reset_IBUF (reset_IBUF)
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INV:I->O 155 0.704 1.301 reset_inv1_INV_0 (reset_inv)
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FDR:R 0.911 w_st
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----------------------------------------
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Total 4.803ns (2.833ns logic, 1.970ns route)
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(59.0% logic, 41.0% route)
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=========================================================================
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Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'
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Total number of paths / destination ports: 169 / 11
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-------------------------------------------------------------------------
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Offset: 9.916ns (Levels of Logic = 5)
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Source: buffer_addr_0 (FF)
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Destination: sram_data<2> (PAD)
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Source Clock: clk falling
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Data Path: buffer_addr_0 to sram_data<2>
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Gate Net
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Cell:in->out fanout Delay Delay Logical Name (Net Name)
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---------------------------------------- ------------
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FD_1:C->Q 5 0.591 0.808 buffer_addr_0 (buffer_addr_0)
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LUT2:I0->O 2 0.704 0.482 UART/if_arm1/data_out_or000111 (N6)
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LUT4:I2->O 8 0.704 0.932 UART/if_arm1/data_out<0>11 (N01)
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LUT4:I0->O 1 0.704 0.595 UART/if_arm1/data_out<2>4 (UART/if_arm1/data_out<2>4)
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LUT4:I0->O 1 0.704 0.420 UART/if_arm1/data_out<2>14 (rdBus<2>)
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IOBUF:I->IO 3.272 sram_data_2_IOBUF (sram_data<2>)
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----------------------------------------
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Total 9.916ns (6.679ns logic, 3.237ns route)
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(67.4% logic, 32.6% route)
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=========================================================================
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Timing constraint: Default path analysis
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Total number of paths / destination ports: 16 / 8
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-------------------------------------------------------------------------
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Delay: 6.573ns (Levels of Logic = 3)
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Source: ncs (PAD)
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Destination: sram_data<7> (PAD)
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Data Path: ncs to sram_data<7>
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Gate Net
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Cell:in->out fanout Delay Delay Logical Name (Net Name)
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---------------------------------------- ------------
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IBUF:I->O 2 1.218 0.622 ncs_IBUF (ncs_IBUF)
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LUT2:I0->O 8 0.704 0.757 T1 (T)
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IOBUF:T->IO 3.272 sram_data_7_IOBUF (sram_data<7>)
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----------------------------------------
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Total 6.573ns (5.194ns logic, 1.379ns route)
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(79.0% logic, 21.0% route)
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|
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=========================================================================
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|
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Total REAL time to Xst completion: 28.00 secs
|
|
Total CPU time to Xst completion: 24.17 secs
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-->
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Total memory usage is 143224 kilobytes
|
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|
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Number of errors : 0 ( 0 filtered)
|
|
Number of warnings : 49 ( 0 filtered)
|
|
Number of infos : 1 ( 0 filtered)
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