65 lines
2.4 KiB
Plaintext
65 lines
2.4 KiB
Plaintext
Release 10.1.03 Map K.39 (lin)
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Xilinx Map Application Log File for Design 'uart_peripheral'
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Design Information
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------------------
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Command Line : map -pr b -p xc3s500e-VQ100-4 project.ngd
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Target Device : xc3s500e
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Target Package : vq100
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Target Speed : -4
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Mapper Version : spartan3e -- $Revision: 1.46.12.2 $
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Mapped Date : Thu Nov 11 14:37:58 2010
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Mapping design into LUTs...
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Writing file project.ngm...
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Running directed packing...
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Running delay-based LUT packing...
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Running related packing...
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Writing design file "project.ncd"...
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Design Summary
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--------------
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Design Summary:
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Number of errors: 0
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Number of warnings: 2
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Logic Utilization:
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Number of Slice Flip Flops: 157 out of 9,312 1%
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Number of 4 input LUTs: 141 out of 9,312 1%
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Logic Distribution:
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Number of occupied Slices: 138 out of 4,656 2%
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Number of Slices containing only related logic: 138 out of 138 100%
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Number of Slices containing unrelated logic: 0 out of 138 0%
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*See NOTES below for an explanation of the effects of unrelated logic.
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Total Number of 4 input LUTs: 181 out of 9,312 1%
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Number used as logic: 141
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Number used as a route-thru: 40
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Number of bonded IOBs: 20 out of 66 30%
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IOB Flip Flops: 16
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Number of BUFGMUXs: 1 out of 24 4%
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Peak Memory Usage: 152 MB
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Total REAL time to MAP completion: 10 secs
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Total CPU time to MAP completion: 8 secs
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NOTES:
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Related logic is defined as being logic that shares connectivity - e.g. two
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LUTs are "related" if they share common inputs. When assembling slices,
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Map gives priority to combine logic that is related. Doing so results in
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the best timing performance.
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Unrelated logic shares no connectivity. Map will only begin packing
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unrelated logic into a slice once 99% of the slices are occupied through
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related logic packing.
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Note that once logic distribution reaches the 99% level through related
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logic packing, this does not mean the device is completely utilized.
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Unrelated logic packing will then begin, continuing until all usable LUTs
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and FFs are occupied. Depending on your timing budget, increased levels of
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unrelated logic packing may adversely affect the overall timing performance
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of your design.
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Mapping completed.
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See MAP report file "project.mrp" for details.
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