208 lines
13 KiB
Plaintext
208 lines
13 KiB
Plaintext
Release 10.1.03 Map K.39 (lin)
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Xilinx Mapping Report File for Design 'uart_peripheral'
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Design Information
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------------------
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Command Line : map -pr b -p xc3s500e-VQ100-4 project.ngd
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Target Device : xc3s500e
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Target Package : vq100
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Target Speed : -4
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Mapper Version : spartan3e -- $Revision: 1.46.12.2 $
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Mapped Date : Thu Nov 11 14:37:58 2010
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Design Summary
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--------------
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Number of errors: 0
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Number of warnings: 2
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Logic Utilization:
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Number of Slice Flip Flops: 157 out of 9,312 1%
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Number of 4 input LUTs: 141 out of 9,312 1%
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Logic Distribution:
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Number of occupied Slices: 138 out of 4,656 2%
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Number of Slices containing only related logic: 138 out of 138 100%
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Number of Slices containing unrelated logic: 0 out of 138 0%
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*See NOTES below for an explanation of the effects of unrelated logic.
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Total Number of 4 input LUTs: 181 out of 9,312 1%
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Number used as logic: 141
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Number used as a route-thru: 40
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Number of bonded IOBs: 20 out of 66 30%
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IOB Flip Flops: 16
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Number of BUFGMUXs: 1 out of 24 4%
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Peak Memory Usage: 152 MB
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Total REAL time to MAP completion: 10 secs
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Total CPU time to MAP completion: 8 secs
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NOTES:
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Related logic is defined as being logic that shares connectivity - e.g. two
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LUTs are "related" if they share common inputs. When assembling slices,
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Map gives priority to combine logic that is related. Doing so results in
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the best timing performance.
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Unrelated logic shares no connectivity. Map will only begin packing
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unrelated logic into a slice once 99% of the slices are occupied through
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related logic packing.
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Note that once logic distribution reaches the 99% level through related
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logic packing, this does not mean the device is completely utilized.
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Unrelated logic packing will then begin, continuing until all usable LUTs
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and FFs are occupied. Depending on your timing budget, increased levels of
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unrelated logic packing may adversely affect the overall timing performance
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of your design.
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Table of Contents
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-----------------
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Section 1 - Errors
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Section 2 - Warnings
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Section 3 - Informational
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Section 4 - Removed Logic Summary
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Section 5 - Removed Logic
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Section 6 - IOB Properties
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Section 7 - RPMs
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Section 8 - Guide Report
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Section 9 - Area Group and Partition Summary
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Section 10 - Modular Design Summary
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Section 11 - Timing Report
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Section 12 - Configuration String Information
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Section 13 - Control Set Information
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Section 14 - Utilization by Hierarchy
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Section 1 - Errors
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------------------
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Section 2 - Warnings
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--------------------
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WARNING:LIT:243 - Logical network RxD2 has no load.
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WARNING:LIT:395 - The above warning message base_net_load_rule is repeated 1
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more times for the following (max. 5 shown):
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TxD2
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To see the details of these warning messages, please use the -detail switch.
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Section 3 - Informational
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-------------------------
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INFO:MapLib:564 - The following environment variables are currently set:
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INFO:MapLib:591 - XIL_MAP_LOCWARN Value: 1
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INFO:LIT:244 - All of the single ended outputs in this design are using slew
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rate limited output drivers. The delay on speed critical single ended outputs
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can be dramatically reduced by designating them as fast outputs.
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Section 4 - Removed Logic Summary
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---------------------------------
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2 block(s) optimized away
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Section 5 - Removed Logic
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-------------------------
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Optimized Block(s):
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TYPE BLOCK
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GND XST_GND
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VCC XST_VCC
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To enable printing of redundant blocks removed and signals merged, set the
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detailed map report option and rerun map.
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Section 6 - IOB Properties
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--------------------------
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+-------------------------------------------------------------------------------------------------------------------------------------------------+
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| IOB Name | Type | Direction | IO Standard | Drive | Slew | Reg (s) | Resistor | IOB |
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| | | | | Strength | Rate | | | Delay |
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+-------------------------------------------------------------------------------------------------------------------------------------------------+
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| RxD | IBUF | INPUT | LVCMOS25 | | | IFF1 | | 0 / 3 |
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| TxD | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | OFF1 | | 0 / 0 |
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| addr<0> | IBUF | INPUT | LVCMOS25 | | | IFF1 | | 0 / 3 |
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| addr<1> | IBUF | INPUT | LVCMOS25 | | | IFF1 | | 0 / 3 |
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| addr<2> | IBUF | INPUT | LVCMOS25 | | | IFF1 | | 0 / 3 |
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| clk | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 |
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| irq_pin | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 |
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| led | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | OFF1 | | 0 / 0 |
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| ncs | IBUF | INPUT | LVCMOS25 | | | IFF1 | | 0 / 3 |
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| noe | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 |
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| nwe | IBUF | INPUT | LVCMOS25 | | | IFF1 | | 0 / 3 |
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| reset | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 |
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| sram_data<0> | IOB | BIDIR | LVCMOS25 | 12 | SLOW | IFF1 | | 0 / 3 |
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| sram_data<1> | IOB | BIDIR | LVCMOS25 | 12 | SLOW | IFF1 | | 0 / 3 |
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| sram_data<2> | IOB | BIDIR | LVCMOS25 | 12 | SLOW | IFF1 | | 0 / 3 |
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| sram_data<3> | IOB | BIDIR | LVCMOS25 | 12 | SLOW | IFF1 | | 0 / 3 |
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| sram_data<4> | IOB | BIDIR | LVCMOS25 | 12 | SLOW | IFF1 | | 0 / 3 |
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| sram_data<5> | IOB | BIDIR | LVCMOS25 | 12 | SLOW | IFF1 | | 0 / 3 |
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| sram_data<6> | IOB | BIDIR | LVCMOS25 | 12 | SLOW | IFF1 | | 0 / 3 |
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| sram_data<7> | IOB | BIDIR | LVCMOS25 | 12 | SLOW | IFF1 | | 0 / 3 |
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+-------------------------------------------------------------------------------------------------------------------------------------------------+
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Section 7 - RPMs
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----------------
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Section 8 - Guide Report
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------------------------
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Guide not run on this design.
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Section 9 - Area Group and Partition Summary
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--------------------------------------------
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Partition Implementation Status
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-------------------------------
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No Partitions were found in this design.
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-------------------------------
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Area Group Information
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----------------------
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No area groups were found in this design.
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----------------------
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Section 10 - Modular Design Summary
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-----------------------------------
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Modular Design not used for this design.
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Section 11 - Timing Report
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--------------------------
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This design was not run using timing mode.
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Section 12 - Configuration String Details
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-----------------------------------------
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Use the "-detail" map option to print out Configuration Strings
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Section 13 - Control Set Information
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------------------------------------
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No control set information for this architecture.
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Section 14 - Utilization by Hierarchy
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-------------------------------------
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+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
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| Module | Partition | Slices | Slice Reg | LUTs | LUTRAM | BRAM | MULT18X18 | BUFG | DCM | Full Hierarchical Name |
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+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
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| uart_peripheral/ | | 35/165 | 34/157 | 47/181 | 0/0 | 0/0 | 0/0 | 1/1 | 0/0 | uart_peripheral |
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| +UART | | 0/130 | 0/123 | 0/134 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | uart_peripheral/UART |
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| ++buffrx1 | | 14/14 | 20/20 | 5/5 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | uart_peripheral/UART/buffrx1 |
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| ++bufftx1 | | 12/12 | 17/17 | 14/14 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | uart_peripheral/UART/bufftx1 |
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| ++ctrl_rx1 | | 3/3 | 5/5 | 6/6 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | uart_peripheral/UART/ctrl_rx1 |
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| ++ctrl_tx1 | | 6/6 | 6/6 | 10/10 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | uart_peripheral/UART/ctrl_tx1 |
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| ++dato_rdy1 | | 3/3 | 2/2 | 2/2 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | uart_peripheral/UART/dato_rdy1 |
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| ++div161 | | 3/3 | 4/4 | 4/4 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | uart_peripheral/UART/div161 |
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| ++div27 | | 5/5 | 6/6 | 9/9 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | uart_peripheral/UART/div27 |
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| ++div_ms1 | | 31/31 | 33/33 | 27/27 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | uart_peripheral/UART/div_ms1 |
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| ++ier1 | | 3/3 | 3/3 | 2/2 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | uart_peripheral/UART/ier1 |
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| ++if_arm1 | | 18/18 | 0/0 | 30/30 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | uart_peripheral/UART/if_arm1 |
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| ++ifrxd1 | | 1/1 | 2/2 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | uart_peripheral/UART/ifrxd1 |
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| ++isr1 | | 14/14 | 8/8 | 13/13 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | uart_peripheral/UART/isr1 |
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| ++lcr1 | | 4/4 | 8/8 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | uart_peripheral/UART/lcr1 |
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| ++muestreo1 | | 7/7 | 6/6 | 8/8 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | uart_peripheral/UART/muestreo1 |
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| ++pulso1 | | 2/2 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | uart_peripheral/UART/pulso1 |
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| ++pulso2 | | 2/2 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | uart_peripheral/UART/pulso2 |
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| ++pulso3 | | 2/2 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | uart_peripheral/UART/pulso3 |
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+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
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* Slices can be packed with basic elements from multiple hierarchies.
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Therefore, a slice will be counted in every hierarchical module
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that each of its packed basic elements belong to.
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** For each column, there are two numbers reported <A>/<B>.
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<A> is the number of elements that belong to that specific hierarchical module.
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<B> is the total number of elements from that hierarchical module and any lower level
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hierarchical modules below.
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*** The LUTRAM column counts all LUTs used as memory including RAM, ROM, and shift registers.
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