mirror of
git://projects.qi-hardware.com/nn-usb-fpga.git
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435 lines
9.8 KiB
Plaintext
435 lines
9.8 KiB
Plaintext
EESchema Schematic File Version 2
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LIBS:power,device,conn,linear,regul,74xx,cmos4000,adc-dac,memory,xilinx,special,microcontrollers,dsp,microchip,analog_switches,motorola,texas,intel,audio,interface,digital-audio,philips,display,cypress,siliconi,contrib,valves,./SAKC.cache
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EELAYER 24 0
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EELAYER END
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$Descr A4 11700 8267
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Sheet 1 9
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Title ""
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Date "23 feb 2010"
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Rev ""
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Comp ""
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Comment1 ""
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Comment2 ""
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Comment3 ""
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Comment4 ""
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$EndDescr
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Wire Wire Line
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3690 2960 4310 2960
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Wire Wire Line
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3910 2810 3690 2810
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Wire Wire Line
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3190 2750 2550 2750
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Wire Wire Line
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3190 2690 2550 2690
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Wire Wire Line
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2550 2630 3190 2630
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Wire Wire Line
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3990 4130 4310 4130
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Wire Wire Line
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3990 4070 4310 4070
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Wire Wire Line
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3990 4010 4310 4010
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Wire Wire Line
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3990 3950 4310 3950
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Wire Wire Line
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4030 3530 4310 3530
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Wire Wire Line
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4030 3470 4310 3470
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Wire Wire Line
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4030 3410 4310 3410
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Wire Wire Line
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3690 2900 4310 2900
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Wire Wire Line
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3690 2840 4310 2840
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Wire Wire Line
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6190 3660 6530 3660
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Wire Wire Line
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6190 3600 6530 3600
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Wire Wire Line
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6530 3540 6190 3540
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Wire Wire Line
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6530 3210 6190 3210
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Wire Wire Line
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6530 3150 6190 3150
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Wire Wire Line
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6530 3090 6190 3090
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Wire Wire Line
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6530 3030 6190 3030
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Wire Wire Line
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6530 2970 6190 2970
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Wire Wire Line
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6530 2850 6190 2850
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Wire Wire Line
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6530 2790 6190 2790
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Wire Bus Line
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2550 2820 2740 2820
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Wire Bus Line
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2740 2820 2740 3880
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Wire Bus Line
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2740 3880 3490 3880
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Wire Bus Line
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6530 2670 6190 2670
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Wire Bus Line
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4030 3380 4310 3380
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Wire Bus Line
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3690 2630 4310 2630
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Wire Bus Line
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3690 2660 4310 2660
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Wire Bus Line
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6530 2640 6190 2640
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Wire Bus Line
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3190 2890 2920 2890
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Wire Bus Line
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2920 2890 2920 3910
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Wire Bus Line
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2920 3910 3490 3910
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Wire Wire Line
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6190 2820 6530 2820
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Wire Wire Line
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6190 2880 6530 2880
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Wire Wire Line
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6190 2940 6530 2940
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Wire Wire Line
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6190 3000 6530 3000
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Wire Wire Line
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6190 3060 6530 3060
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Wire Wire Line
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6190 3120 6530 3120
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Wire Wire Line
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6190 3180 6530 3180
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Wire Wire Line
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6190 3240 6530 3240
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Wire Wire Line
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6190 3570 6530 3570
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Wire Wire Line
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6530 3630 6190 3630
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Wire Wire Line
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6530 3690 6190 3690
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Wire Wire Line
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4310 2870 3690 2870
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Wire Wire Line
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4310 2930 3690 2930
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Wire Wire Line
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4310 3440 4030 3440
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Wire Wire Line
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4310 3500 4030 3500
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Wire Wire Line
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4310 3560 4030 3560
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Wire Wire Line
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4310 3980 3990 3980
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Wire Wire Line
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4310 4040 3990 4040
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Wire Wire Line
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4310 4100 3990 4100
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Wire Wire Line
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3190 2600 2550 2600
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Wire Wire Line
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2550 2660 3190 2660
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Wire Wire Line
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2550 2720 3190 2720
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Wire Wire Line
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6310 2910 6190 2910
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Text GLabel 7360 4020 2 20 BiDi
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GND
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Text GLabel 7030 3630 2 20 BiDi
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GND
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Text GLabel 7030 3210 2 20 BiDi
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GND
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Text GLabel 3490 4130 0 20 BiDi
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GND
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Text GLabel 3530 3520 0 20 BiDi
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GND
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Text GLabel 2050 2790 0 20 BiDi
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GND
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Text GLabel 3190 2950 0 20 BiDi
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GND
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Text GLabel 6190 3920 2 20 BiDi
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GND
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Text Label 6310 2910 0 20 ~
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CS2_N
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Text Label 3910 2810 0 20 ~
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CS2_N
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Text GLabel 6530 2760 0 20 BiDi
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RDWR_N
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$Sheet
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S 4310 2480 1880 1750
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U 4B8F65CC
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F0 "CPU" 60
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F1 "CPU.sch" 60
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F2 "D[0..15]" B L 4310 2660 20
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F3 "TCK_F" B L 4310 2870 20
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F4 "NF_ALE" B R 6190 2850 20
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F5 "NF_CLE" B R 6190 2880 20
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F6 "FWE_N" B R 6190 2820 20
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F7 "FRE_N" B R 6190 2970 20
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F8 "FRB_N" B R 6190 3000 20
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F9 "SD_CD_N" B R 6190 3150 20
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F10 "CS2_N" B R 6190 2910 20
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F11 "CS1_N" B R 6190 2940 20
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F12 "RXD" B R 6190 3660 20
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F13 "TXD" B R 6190 3690 20
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F14 "MSC_D0" B R 6190 3240 20
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F15 "DM0" B R 6190 3570 20
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F16 "DP0" B R 6190 3540 20
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F17 "WE1_N" B L 4310 2720 20
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F18 "TDI_F" B L 4310 2840 20
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F19 "TMS_F" B L 4310 2930 20
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F20 "TDO_F" B L 4310 2900 20
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F21 "SCK" B R 6190 3630 20
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F22 "SDA" B R 6190 3600 20
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F23 "MSC_CLK" B R 6190 3210 20
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F24 "MSC_CMD" B R 6190 3180 20
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F25 "ADIN0" B L 4310 4070 20
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F26 "ADIN1" B L 4310 4040 20
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F27 "R-HPO" B L 4310 4100 20
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F28 "L-HPO" B L 4310 4010 20
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F29 "VRTC" B R 6190 3950 20
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F30 "VDDIO" B R 6190 3980 20
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F31 "VDDPLL" B R 6190 4010 20
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F32 "VDDHP" B R 6190 4040 20
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F33 "VDDUSB" B R 6190 4070 20
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F34 "VDDADC" B R 6190 4100 20
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F35 "VDDCORE" B R 6190 4130 20
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F36 "A[0..14]" B L 4310 2630 20
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F37 "CKE" B R 6190 2790 20
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F38 "CK0" B R 6190 3120 20
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F39 "WE0_N" B L 4310 2750 20
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F40 "RDWR_N" B L 4310 2780 20
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F41 "CAS_N" B R 6190 3030 20
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F42 "RAS_N" B R 6190 3060 20
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F43 "DCS0_N" B R 6190 3090 20
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F44 "LCD_CLK" B L 4310 3410 20
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F45 "LCD_D[0..17]" B L 4310 3380 20
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F46 "LCD_DE" B L 4310 3500 20
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F47 "LCD_HSYNC" B L 4310 3470 20
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F48 "LCD_VSYNC" B L 4310 3440 20
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F49 "LCD_SDA" B L 4310 3560 20
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F50 "LCD_SCL" B L 4310 3530 20
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F51 "LCD_CS" B L 4310 3310 20
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F52 "LCD_RST" B L 4310 3280 20
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F53 "MICIN" B L 4310 3950 20
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F54 "R-LINEIN" B L 4310 3980 20
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F55 "L-LINEIN" B L 4310 4130 20
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F56 "1.8V" B R 6190 4190 20
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F57 "3.3V" B R 6190 4160 20
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F58 "A[0..14]" B R 6190 2640 20
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F59 "D[0..15]" B R 6190 2670 20
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F60 "GND" B R 6190 3920 20
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F61 "IRQ_F" B L 4310 2960 20
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$EndSheet
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$Sheet
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S 6860 3850 500 190
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U 4B8F6097
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F0 "POWER_SUPPLY" 20
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F1 "POWER_SUPPLY.sch" 20
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F2 "BAT_V" B R 7360 3990 20
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F3 "2V5" B R 7360 3910 20
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F4 "2.5V" B L 6860 3920 20
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F5 "1V2" B R 7360 3950 20
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F6 "1.2V" B L 6860 4000 20
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F7 "1.8V" B L 6860 3960 20
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F8 "3V3" B R 7360 3880 20
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F9 "3.3V" B L 6860 3880 20
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F10 "GND" B R 7360 4020 20
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$EndSheet
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$Sheet
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S 6530 3510 500 210
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U 4B8F601F
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F0 "UART_USB_I2C" 20
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F1 "UART_USB_I2C.sch" 20
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F2 "BAT_V" B R 7030 3690 20
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F3 "DP0" B L 6530 3540 20
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F4 "DM0" B L 6530 3570 20
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F5 "SDA" B L 6530 3600 20
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F6 "SCK" B L 6530 3630 20
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F7 "RXD" B L 6530 3660 20
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F8 "TXD" B L 6530 3690 20
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F9 "3.3V" B R 7030 3660 20
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F10 "GND" B R 7030 3630 20
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$EndSheet
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$Sheet
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S 2050 2580 500 270
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U 4B8F5F86
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F0 "AD_CONVERTER" 20
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F1 "D_CONVERTER.sch" 20
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F2 "ANALOG[0..7]" B R 2550 2820 20
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F3 "3.3V" B L 2050 2820 20
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F4 "AN_GND" B R 2550 2780 20
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F5 "ADC_EOC" B R 2550 2750 20
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F6 "ADC_CS" B R 2550 2630 20
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F7 "ADC_CSTART" B R 2550 2600 20
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F8 "ADC_SCLK" B R 2550 2720 20
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F9 "ADC_SDIN" B R 2550 2690 20
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F10 "ADC_SDOUT" B R 2550 2660 20
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F11 "GND" B L 2050 2790 20
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$EndSheet
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$Sheet
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S 6530 2610 500 670
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U 4B8F5CEF
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F0 "MEMORY" 20
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F1 "MEMORY.sch" 20
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F2 "D[0..15]" B L 6530 2670 20
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F3 "WE1_N" B L 6530 2700 20
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F4 "WE0_N" B L 6530 2730 20
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F5 "RDWR_N" B L 6530 2760 20
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F6 "CKE" B L 6530 2790 20
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F7 "FWE_N" B L 6530 2820 20
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F8 "NF_ALE" B L 6530 2850 20
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F9 "NF_CLE" B L 6530 2880 20
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F10 "CS1_N" B L 6530 2940 20
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F11 "FRE_N" B L 6530 2970 20
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F12 "FRB_N" B L 6530 3000 20
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F13 "A[0..14]" B L 6530 2640 20
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F14 "CAS_N" B L 6530 3030 20
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F15 "RAS_N" B L 6530 3060 20
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F16 "DCS0_N" B L 6530 3090 20
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F17 "CK0" B L 6530 3120 20
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F18 "3.3V" B R 7030 3240 20
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F19 "SD_CD_N" B L 6530 3150 20
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F20 "MSC_CMD" B L 6530 3180 20
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F21 "MSC_CLK" B L 6530 3210 20
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F22 "MSC_D0" B L 6530 3240 20
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F23 "GND" B R 7030 3210 20
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$EndSheet
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$Sheet
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S 3490 3840 500 360
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U 4B8F5BC1
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F0 "CONNECTORS" 20
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F1 "CONNECTORS.sch" 20
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F2 "ANALOG[0..7]" B L 3490 3880 20
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F3 "DIG[0..23]" B L 3490 3910 20
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F4 "3.3V" B L 3490 4160 20
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F5 "MICIN" B R 3990 3950 20
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F6 "R-LINEIN" B R 3990 3980 20
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F7 "L-HPO" B R 3990 4010 20
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F8 "ADIN1" B R 3990 4040 20
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F9 "ADIN0" B R 3990 4070 20
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F10 "R-HPO" B R 3990 4100 20
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F11 "L-LINEIN" B R 3990 4130 20
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F12 "AN_GND" B R 3990 4160 20
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F13 "GND" B L 3490 4130 20
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$EndSheet
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Text GLabel 3690 2690 2 20 BiDi
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OSC_XM
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$Sheet
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S 3190 2570 500 450
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U 4B8F57B1
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F0 "FPGA" 20
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F1 "FPGA.sch" 20
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F2 "DIG[0..23]" B L 3190 2890 20
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F3 "A[0..14]" B R 3690 2630 20
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F4 "D[0..7]" B R 3690 2660 20
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F5 "OSC_XM" B R 3690 2690 20
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F6 "3V3" B L 3190 2780 20
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F7 "2V5" B L 3190 2810 20
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F8 "1V2" B L 3190 2840 20
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F9 "WE1_N" B R 3690 2720 20
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F10 "WE0_N" B R 3690 2750 20
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F11 "RDWR_N" B R 3690 2780 20
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F12 "CS2_N" B R 3690 2810 20
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F13 "TDI_F" B R 3690 2840 20
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F14 "TCK_F" B R 3690 2870 20
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F15 "TDO_F" B R 3690 2900 20
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F16 "TMS_F" B R 3690 2930 20
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F17 "ADC_CSTART" B L 3190 2600 20
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F18 "ADC_CS" B L 3190 2630 20
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F19 "ADC_SDOUT" B L 3190 2660 20
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F20 "ADC_SDIN" B L 3190 2690 20
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F21 "ADC_SCLK" B L 3190 2720 20
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F22 "ADC_EOC" B L 3190 2750 20
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F23 "GND" B L 3190 2950 20
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F24 "IRQ_F" B R 3690 2960 20
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$EndSheet
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Text GLabel 4310 3280 0 20 BiDi
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LCD_RST
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Text GLabel 4310 3310 0 20 BiDi
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LCD_CS
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Text GLabel 6190 4130 2 20 BiDi
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VDDCORE
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Text GLabel 6190 4100 2 20 BiDi
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VDDADC
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Text GLabel 6190 4070 2 20 BiDi
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VDDUSB
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Text GLabel 6190 4040 2 20 BiDi
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VDDHP
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Text GLabel 6190 4010 2 20 BiDi
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VDDPLL
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Text GLabel 6190 3980 2 20 BiDi
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VDDIO
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Text GLabel 6190 3950 2 20 BiDi
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VRTC
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Text GLabel 4310 2720 0 20 BiDi
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WE1_N
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Text GLabel 4310 2750 0 20 BiDi
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WE0_N
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Text GLabel 4310 2780 0 20 BiDi
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RDWR_N
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Text GLabel 6190 4190 2 20 BiDi
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1.8V
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Text GLabel 6190 4160 2 20 BiDi
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3.3V
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Text GLabel 3530 3550 0 20 BiDi
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3.3V
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Text GLabel 7360 3910 2 20 BiDi
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2V5
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Text GLabel 6860 3920 0 20 BiDi
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2.5V
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Text GLabel 6860 4000 0 20 BiDi
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1.2V
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Text GLabel 7360 3950 2 20 BiDi
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1V2
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Text GLabel 7360 3880 2 20 BiDi
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3V3
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Text GLabel 6860 3880 0 20 BiDi
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3.3V
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Text GLabel 6860 3960 0 20 BiDi
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1.8V
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Text GLabel 7360 3990 2 20 BiDi
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BAT_V
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Text GLabel 3990 4160 2 20 BiDi
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AN_GND
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Text GLabel 3490 4160 0 20 BiDi
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3.3V
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Text GLabel 7030 3690 2 20 BiDi
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BAT_V
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Text GLabel 7030 3660 2 20 BiDi
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3.3V
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Text GLabel 2550 2780 2 20 BiDi
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AN_GND
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Text GLabel 2050 2820 0 20 BiDi
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3.3V
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Text GLabel 7030 3240 2 20 BiDi
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3.3V
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Text GLabel 6530 2700 0 20 BiDi
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WE1_N
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Text GLabel 6530 2730 0 20 BiDi
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WE0_N
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Text GLabel 3690 2780 2 20 BiDi
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RDWR_N
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Text GLabel 3690 2750 2 20 BiDi
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WE0_N
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Text GLabel 3690 2720 2 20 BiDi
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WE1_N
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Text GLabel 3190 2840 0 20 BiDi
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1V2
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Text GLabel 3190 2810 0 20 BiDi
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2V5
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Text GLabel 3190 2780 0 20 BiDi
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3V3
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$Sheet
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S 3530 3330 500 270
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U 4B782FB9
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F0 "LCD" 30
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F1 "LCD.sch" 30
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F2 "3.3V" B L 3530 3550 20
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F3 "LCD_CLK" B R 4030 3410 20
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F4 "LCD_VSYNC" B R 4030 3440 20
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F5 "LCD_HSYNC" B R 4030 3470 20
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F6 "LCD_DE" B R 4030 3500 20
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F7 "LCD_SCL" B R 4030 3530 20
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F8 "LCD_SDA" B R 4030 3560 20
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F9 "LCD_D[0..7]" B R 4030 3380 20
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F10 "GND" B L 3530 3520 20
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$EndSheet
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$EndSCHEMATC
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