mirror of
git://projects.qi-hardware.com/nn-usb-fpga.git
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a7c692d3f0
Adding FPGA sram hdl code and user space code Fixing some errors: LCD's pinout connector is swapped FPGA TDI SIGNAL must be routed to another pin (C14), right now is DQMH Remove R11 Check JZ4725 symbol's component (PORTD is wrong) Adding PB2 and PB3 wiring ADC's vref to external connector Adding power LED Adding CPU Led
76 lines
1.6 KiB
Verilog
76 lines
1.6 KiB
Verilog
`timescale 1ns / 1ps
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module sram_bus(clk, sram_data, addr, nwe, ncs, noe, reset, led);
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parameter B = (7);
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input clk, addr, nwe, ncs, noe, reset;
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inout [B:0] sram_data;
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output led;
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// Internal conection
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wire led;
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// synchronize signals
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reg sncs, snwe;
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reg [12:0] buffer_addr;
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reg [B:0] buffer_data;
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// interfaz fpga signals
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wire [12:0] addr;
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// bram interfaz signals
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reg we;
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reg w_st;
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reg [B:0] wdBus;
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wire [B:0] rdBus;
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// interefaz signals assignments
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wire T = ~noe | ncs;
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assign sram_data = T?8'bZ:rdBus;
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//--------------------------------------------------------------------------
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// synchronize assignment
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always @(negedge clk)
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begin
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sncs <= ncs;
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snwe <= nwe;
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buffer_data <= sram_data;
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buffer_addr <= addr;
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end
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// write access cpu to bram
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always @(posedge clk)
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if(reset) {w_st, we, wdBus} <= 0;
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else begin
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wdBus <= buffer_data;
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case (w_st)
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0: begin
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we <= 0;
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if(sncs | snwe) w_st <= 1;
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end
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1: begin
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if(~(sncs | snwe)) begin
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we <= 1;
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w_st <= 0;
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end
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else we <= 0;
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end
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endcase
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end
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RAMB16_S18 ba0( .CLK(~clk), .EN(1'b1), .SSR(1'b0), .ADDR(buffer_addr),
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.WE(we), .DIP(2'b00), .DI(wdBus), .DO(rdBus) );
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reg [32:0] counter;
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always @(posedge clk) begin
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if (reset)
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counter <= {32{1'b0}};
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else
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counter <= counter + 1;
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end
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assign led = counter[24];
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endmodule
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