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64 lines
2.8 KiB
Plaintext
64 lines
2.8 KiB
Plaintext
# // ModelSim SE 6.0d Apr 25 2005 Linux 2.6.32-22-generic
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# //
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# // Copyright Mentor Graphics Corporation 2005
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# // All Rights Reserved.
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# //
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# // THIS WORK CONTAINS TRADE SECRET AND
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# // PROPRIETARY INFORMATION WHICH IS THE PROPERTY
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# // OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS
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# // AND IS SUBJECT TO LICENSE TERMS.
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# //
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# do sram_bus_TIMING_TB.do
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# ** Warning: (vlib-34) Library already exists at "work".
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# Model Technology ModelSim SE vlog 6.0d Compiler 2005.04 Apr 25 2005
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# -- Compiling module sram_bus
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# -- Compiling module glbl
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# -- Compiling module sram_bus_TB_v
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# ** Warning: glbl.v(5): 'glbl' already exists.
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# -- Compiling module glbl
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#
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# Top level modules:
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# glbl
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# sram_bus_TB_v
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# vsim -L simprims_ver -L unisims_ver -L xilinxcorelib_ver -t 1ps sram_bus_TB_v glbl
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# Loading work.sram_bus_TB_v
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# Loading work.sram_bus
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# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_ONE
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# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_ZERO
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# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_FF
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# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_SFF
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# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_MUX2
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# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_XOR2
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# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_LUT2
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# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_BUF
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# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_LUT3
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# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_INV
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# Refreshing /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_RAMB16_S2
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# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_RAMB16_S2
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# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_BPAD
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# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_IPAD
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# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_OPAD
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# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_CKBUF
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# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_OBUFT
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# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_OBUF
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# Loading work.glbl
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# ** Warning: (vsim-3017) ../sram_bus_TB.v(21): [TFMPC] - Too few port connections. Expected 8, found 7.
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# Region: /sram_bus_TB_v/uut
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# ** Warning: (vsim-3015) ../sram_bus_TB.v(21): [PCDPC] - Port size (8 or 8) does not match connection size (1) for port 'sram_data'.
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# Region: /sram_bus_TB_v/uut
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# ** Warning: (vsim-3722) ../sram_bus_TB.v(21): [TFMPC] - Missing connection for port 'led'.
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# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.ffsrce
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# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.sffsrce
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# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.mux
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# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.x_lut2_mux4
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# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.x_lut3_mux4
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# .main_pane.mdi.interior.cs.vm.paneset.cli_0.wf.clip.cs
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# .main_pane.workspace
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# .main_pane.signals.interior.cs
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exit
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