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95 lines
3.2 KiB
Verilog
95 lines
3.2 KiB
Verilog
// =============================================================================
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// COPYRIGHT NOTICE
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// Copyright 2006 (c) Lattice Semiconductor Corporation
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// ALL RIGHTS RESERVED
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// This confidential and proprietary software may be used only as authorised by
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// a licensing agreement from Lattice Semiconductor Corporation.
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// The entire notice above must be reproduced on all authorized copies and
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// copies may only be made to the extent permitted by a licensing agreement from
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// Lattice Semiconductor Corporation.
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//
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// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada)
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// 5555 NE Moore Court 408-826-6000 (other locations)
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// Hillsboro, OR 97124 web : http://www.latticesemi.com/
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// U.S.A email: techsupport@latticesemi.com
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// =============================================================================/
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// FILE DETAILS
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// Project : LatticeMico32
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// File : lm32_multiplier.v
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// Title : Pipelined multiplier.
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// Dependencies : lm32_include.v
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// Version : 6.1.17
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// =============================================================================
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`include "lm32_include.v"
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/////////////////////////////////////////////////////
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// Module interface
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/////////////////////////////////////////////////////
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module lm32_multiplier (
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// ----- Inputs -----
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clk_i,
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rst_i,
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stall_x,
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stall_m,
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operand_0,
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operand_1,
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// ----- Ouputs -----
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result
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);
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/////////////////////////////////////////////////////
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// Inputs
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/////////////////////////////////////////////////////
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input clk_i; // Clock
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input rst_i; // Reset
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input stall_x; // Stall instruction in X stage
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input stall_m; // Stall instruction in M stage
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input [`LM32_WORD_RNG] operand_0; // Muliplicand
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input [`LM32_WORD_RNG] operand_1; // Multiplier
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/////////////////////////////////////////////////////
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// Outputs
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/////////////////////////////////////////////////////
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output [`LM32_WORD_RNG] result; // Product of multiplication
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reg [`LM32_WORD_RNG] result;
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/////////////////////////////////////////////////////
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// Internal nets and registers
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/////////////////////////////////////////////////////
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reg [`LM32_WORD_RNG] muliplicand;
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reg [`LM32_WORD_RNG] multiplier;
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reg [`LM32_WORD_RNG] product;
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/////////////////////////////////////////////////////
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// Sequential logic
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/////////////////////////////////////////////////////
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always @(posedge clk_i `CFG_RESET_SENSITIVITY)
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begin
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if (rst_i == `TRUE)
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begin
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muliplicand <= {`LM32_WORD_WIDTH{1'b0}};
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multiplier <= {`LM32_WORD_WIDTH{1'b0}};
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product <= {`LM32_WORD_WIDTH{1'b0}};
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result <= {`LM32_WORD_WIDTH{1'b0}};
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end
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else
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begin
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if (stall_x == `FALSE)
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begin
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muliplicand <= operand_0;
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multiplier <= operand_1;
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end
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if (stall_m == `FALSE)
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product <= muliplicand * multiplier;
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result <= product;
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end
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end
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endmodule
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