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17 lines
292 B
Verilog
17 lines
292 B
Verilog
`timescale 1ns / 1ps
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module blink(clk, reset, led);
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input clk, reset;
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output led;
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reg [24:0] counter;
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always @(posedge clk) begin
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if (~reset)
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counter <= {25{1'b0}};
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else
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counter <= counter + 1;
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end
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assign led = counter[24];
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endmodule
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