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nn-usb-fpga/Examples/sram/logic/simulation/sram_bus_TIMING_TB.do
2010-05-12 09:36:30 -05:00

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vlib work
vlog -incr "../build/project.v" "../sram_bus_TB.v" "glbl.v"
vsim -t 1ps -L simprims_ver -L unisims_ver -L xilinxcorelib_ver sram_bus_TB glbl
view wave
#do wave.do
add wave *
view structure
view signals
run 5us